Vlsi Technology, Inc.

Pericom Semiconductor Corporation

Belle Wong

Derwin W Mattos

Anthony Yap Wong

Donald M Lee

Charles Hsiao

Michael B Cheng

A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable. Clock-enable conditioning to prevent partial output pulses is merged with the synchronizing function to further reduce latency.

Meta-stable-resistant front-end to a synchronizer with asynchronous

A circuit for producing a buffered output includes a power source, a ground, a circuit input, a circuit output, a voltage reference source, a current control pre-driver and an output driver. The circuit input receives an input signal. The circuit output produces an output signal. The voltage reference source generates a reference voltage. The current control pre-driver includes a first current source, a second current source, and control logic. The first current source is connected to the power source and has a first control input. The second current source is connected to the ground and has a second control input. The control logic is connected to the circuit input, to the voltage reference source, to the first control input of the first current source and to the second control input of the second current source. In response to a first voltage value of the input signal on the circuit input, the control logic turns off the second current source and turns on the first current source. The first current source is turned on by connecting the reference voltage to the first control input of the first current source. In response to a second voltage value of the input signal on the circuit input, the control logic turns off the first current source and turns on the second current source. The second current source is turned on by connecting the reference voltage to the second control input of the second current source. The output driver includes driver circuitry and a feedback capacitance. The driver circuitry is connected to the circuit output. The feedback capacitance includes a first end and a second end. The first end is connected to the first current source and to the second current source. The second end is connected to the circuit output.

Output buffer driver with load compensation

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Belle Wong