Adeia Semiconductor Bonding Technologies Inc.

Rambus Inc.

Adeia Semiconductor Technologies LLC

Silicon Pipe, Inc.

Nec Corporation

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Digital Optics Corporation

Tessera Technologies Ireland Limited

Nan Chang O-film Optoelectronics Technology Ltd

Adeia Semiconductor Inc.

Invensas LLC

Xcelsis Corporation

Belgacem Haba

Ilyas Mohammed

Wael Zohni

Richard Dewitt Crisp

Vage Oganesian

Craig S Mitchell

Rajesh Katkar

Cyprian Emeka Uzoh

Piyush Savalia

Javier A DeLaCruz

Masud Beroz

Frank Lambrecht

Teck-Gyu Kang

Ellis Chau

Guilian Gao

Laura Wills Mirkarimi

Philip Damberg

Hiroaki Sato

Giles Humpston

Philip R Osborn

Norihito Masuda

Gaius Gillman Fountain, Jr

Yoichi Kubota

Terrence Caskey

Joseph Charles Fjelstad

David Bazeley Tuckerman

John W Smith

Liang Wang

David Ovrutsky

Kiyoaki Hashimoto

Wei-Shun Wang

Gabriel Z Guevara

Charles Gerard Woychik

Kazuo Sakuma

Zhuowen Sun

Kyong-Mo Bang

Min Tao

Kishor V Desai

David Nguyen

Shaowu Huang

Konstantine N Karavakis

Michael W Newman

Sayeh Khalili

Tomoyuki Kikuchi

Brian Marcucci

Kurosawa Inetaro

Reynaldo Co

Jae M Park

Pezhman Monadgemi

Thomas Workman

Thomas H DiStefano

Arkalgud R Sitaram

Ashok S Prabhu

Bongsub Lee

Ron Zhang

Michael Warner

Kimitaka Endo

Anthony B Faraci

John B Riley, Iii

Yong Qin Chen

Paul M Enquist

Donald Victor Perino

David Noel Light

Jeremy Alfred Theil

Kenneth Allen Honer

Michael James Nystrom

Thomas Francis Fox

Richard E Warmke

Xingchao C Yuan

Jesse B Thompson

Stuart E Wilson

Charles Rosenstein

Christopher M Pickett

Ely K Tsern

Richard E Perego

Hong Shen

Billy Wayne Garrett, Jr

Ravindranath T Kollipara

Young-Gon Kim

Ronald Patrick Green

Vernon Solberg

Craig Edward Hampel

Stephen L Morein

Jung Ko

Yukio Morishige

Moti Margalit

Para Kanagasabai Segaram

Moshe Kriman

David A Gibson

Para K Segaram

Akash Agrawal

Andrey Grinman

Donald R Mullen

Lubomyr Taras Romankiw

Ming Li

Arunava Gupta

David Edward Fisch

Kazumi Sugai

Hamid Eslampour

David W Wallis

Adeia Celebrates Semiconductor Technology Pioneer, Dr. Belgacem Haba, who has helped Revolutionize the Semiconductor Industry with Groundbreaking Inventions

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

Stacked devices and methods of fabrication

A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.

Embedded cooling systems for advanced device packaging and methods of manufacturing the same

A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.

Electronic device cooling structures bonded to semiconductor elements

Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

Microelectronic assemblies

A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a first side, a second side vertically adjacent to the first side, a first inlet, a first cavity, and a first outlet. The first side of the cold plate comprises a first region, a second region, and a third region, wherein the second region is between the first region and the third region. In some embodiments, the semiconductor device is attached to the first region of the cold plate and the third region of the cold plate, and the first cavity extends along the second region of the cold plate.

Cold plate cavity designs for improved thermal performance

A bonded structure is disclosed. The bonded structure can include an interconnect structure. The bonded structure can also include a first die directly bonded to the interconnect structure. The bonded structure can also include a second die mounted to the interconnect structure. The second die is spaced apart from the first die laterally along an upper surface of the interconnect structure. The second die is electrically connected with the first die at least partially through the interconnect structure. The bonded structure can further include a dielectric layer that is disposed over the upper surface of the interconnect structure between the first die and the second die.

Bonded structure with interconnect structure

Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate has a perimeter sidewall, a top portion and pairs of opposing cavity sidewalls. The perimeter sidewall extends downwardly from the top portion to a backside of the semiconductor device to define a perimeter of the cold plate. Each pair of opposing cavity sidewalls extends downwardly from the top portion towards the backside of the semiconductor device to define a coolant chamber volume therebetween. A distance between each pair of opposing cavity sidewalls in a direction parallel with the backside of the semiconductor device defines a width of a corresponding coolant chamber volume and a spacing between adjacent coolant chamber volumes, wherein the ratio of width to spacing is about 1:1.

Fluid channel geometry optimizations to improve cooling efficiency

A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

Circuitry for electrical redundancy in bonded structures

A bonded structure with protective semiconductor elements including a semiconductor element with active circuitry and a protective element including an obstructive layer and/or a protective circuitry layer. The obstructive layer is configured to inhibit external access to at least a portion of the active circuitry. The protective circuitry layer is configured to detect or disrupt external access to the protective element and/or the active circuitry of the semiconductor element. The semiconductor element and the protective element are directly bonded without an adhesive along a bonding interface.

Protective semiconductor elements for bonded structures

A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

Apparatus for non-volatile random access memory stacks

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

Integrated cooling assemblies for advanced device packaging and methods of manufacturing the same

The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Symbiotic network on layers

It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

Integrated voltage regulator and passive components

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

Capacitive coupling in a direct-bonded interface for microelectronic devices

Growing community of inventors

Saratoga, CA, United States of America

Belgacem Haba