Marvell Asia Pte., Ltd.

Inphi Corporation

Marvell International Limited

Belal Helal

Jamal Riani

Karthik S Gopalakrishnan

Jorge Pernillo

Chang-Feng Loi

Yu Liao

Aaron W Buchwald

Mrunmay Talegaonkar

Praveen Prabha

Junyi Sun

James Lawrence Gorecki

Michael Q Le

Guojun Ren

Irene Quek

Amber Tan

Arash Farhoodfar

Michael Lewis Takefman

Chuan-Cheng Cheng

Srinivas Swaminathan

Himanshu Arora

A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.

Network transceiver with clock sharing between dies

The present invention relates to data communication and electrical circuits. More specifically, embodiments of the present invention provide a clock and data recovery (CDR) architecture implementation for high data rate wireline communication links. In an embodiment, a CDR device includes a phase detector, a loop filter, and a fractional-N PLL. The fractional-N PLL generates output clock signal based on output of the loop filter. There are other embodiments as well.

Clock and data recovery devices with fractional-N PLL

In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.

Interleaved successive approximation register analog to digital converter

Some of the embodiments of the present disclosure provide an apparatus comprising a voltage controlled oscillator (VCO) having a first transistor, a first resistor operatively coupled between a first terminal of the first transistor and a first node, a first capacitor operatively coupled between a second terminal of the first transistor and the first node, and a second capacitor operatively coupled to the first node, wherein the first capacitor and the second capacitor forms a capacitive voltage divider. Other embodiments are also described and claimed.

Stress tolerant differential colpitts voltage controlled oscillators

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Santa Clara, CA, United States of America

Belal Helal