Nvidia Corporation

Beibei Ren

Ge Yang

Jun Yang

Charles Chew-Yuen Young

Lei Wang

Stephen Felix

Spencer Montgomery Gold

Hua Chen

Hwong-Kwo Lin

Jing Guo

Eric H Voelkel

Andreas J Gotterba

Haiyan Gong

Karthik Natarajan

Jason Golbus

Zhenye Jiang

Hwong-Kwo (Hank) Lin

Guoqing Ning

A subsystem configured to select the power supply to a static random access memory cell compares the level of a dedicated memory supply voltage to the primary system supply voltage. The subsystem then switches the primary system supply to the SRAM cell when the system voltage is higher than the memory supply voltage with some margin. When the system voltage is lower than the memory supply voltage, with margin, the subsystem switches the memory supply to the SRAM cell. When the system voltage is comparable to the memory supply, the subsystem switches the system voltage to the SRAM cell if performance is a prioritized consideration, but switches the memory supply to the SRAM cell if power reduction is a prioritized consideration. In this manner, the system achieves optimum performance without incurring steady state power losses and avoids timing issues in accessing memory.

Power savings via selection of SRAM power source

Apparatuses and methods are provided for a self-timed dynamic sense amplifier flop circuit, wherein a pulse generating circuit may be adapted to generate at least a first logic signal based, at least in part, on a first evaluation node signal, and a discharge path circuit comprising at least a first transistor within a first stack of transistors may be operatively responsive to the first timing signal.

Self-timed dynamic sense amplifier flop circuit apparatus and method

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Beibei Ren