Intermolecular, Inc.

Globalfoundries Inc.

University of California

Bei Li

Olov B Karlsson

John S Foster

Anh Duong

Sean Barstow

Zhendong Hong

Amol Ramesh Joshi

Usha Raghuram

James Mavrinac

Bin Yang

Dipankar Pramanik

Dengtao Zhao

Mark V Raymond

Clemens Fitz

Ruigang Li

Charlene Chen

Jingang Su

Jianlin Liu

Yan Zhu

Ashley Lacey

Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Circular transmission line methods compatible with combinatorial processing of semiconductors

A method for cleaning platinum residues from a surface of a substrate is provided. The method initiates with exposing the surface to a first solution containing a mixture of nitric acid and hydrochloric acid. Then, the surface is exposed to a second solution containing hydrochloric acid.

Method for cleaning platinum residues on a semiconductor substrate

Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.

High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction

Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices.

High productivity combinatorial workflow for photoresist strip applications

The invention discloses a method for cleaning residues from a semiconductor substrate during a nickel platinum silicidation process. Embodiments of the invention provide a multi-step cleaning process, comprising exposing the substrate to a nitric acid solution after a first anneal, followed by an aqua regia solution after a second anneal. The substrate can be optionally exposed to a hydrochloric acid solution afterward to completely remove any remaining platinum residues.

Process to remove Ni and Pt residues for NiPtSi applications

In one embodiment, a memory device includes a substrate, a tunneling oxide, a silicide nanocrystal floating gate, and a control oxide. The tunneling oxide is positioned upon a first surface of the substrate, the silicide nanocrystal floating gate is positioned upon the tunneling oxide, and the control oxide positioned upon the nanocrystal floating gate.

Nanocrystal memories and methods of forming the same

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Fremont, CA, United States of America

Bei Li