Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Bei Chao Zhang

Juan Boon Tan

Fan Zhang

Liang Choo Hsia

Wuping Liu

John Leonard Sudijono

Yong Kong Siew

Chim Seng Seet

Yeow Kheng Lim

Tae Jong Lee

Alan Cuthbertson

Tong Qing Chen

Haifeng Sheng

Sang Yee Loong

Wenhe Lin

Johnny Widodo

Young Way Teh

Dong Kyun Sohn

Chun Hui Low

Chin Chuan Neo

Vincent Ho

Hong Lim Lee

Qiang Guo

Bo Tao

Luying Du

San Leong Liew

Yong Chiang Ee

Mei Sheng Zhou

Wei Liu

Huang Liu

Shao-fu Sanford Chu

Chung Woh Lai

Eng Hua Lim

Lup San Leong

Liang-Choo Hsia

Peter Chew

Raymond Joy

Kho Liep Chok

Arthur Ang

Xian Bin Wang

Chee Kong Leong

Yasri Yudhistira

Johnny Cham

Boon Meng Seah

Shaoqing Zhang

Lai Lin Clare Yong

Jun Chen

Rajneesh Jaiswal

Zhong Yun Zhu

Haznita Abd Karim

Ravi Sankar Yelamanchi

Jing Hui Li

Shao Beng Law

Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.

Reliable interconnect integration scheme

An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.

Integrated circuit system employing alternating conductive layers

The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Poly profile engineering to modulate spacer induced stress for device enhancement

A method of manufacture of an integrated circuit system includes: fabricating a substrate having an integrated circuit; applying a low-K dielectric layer over the integrated circuit; forming a via and a trench, in the low-K dielectric layer, over the integrated circuit; forming a structure surface by a chemical-mechanical planarization (CMP) process; and applying a direct implant to the structure surface for forming an implant layer and a metal passivation layer including repairing damage, to the low-K dielectric layer, caused by the CMP process.

Integrated circuit system employing low-k dielectrics and method of manufacture thereof

An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.

Apparatus and methods for cleaning and drying of wafers

An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.

Integrated circuit system employing back end of line via techniques

A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

Reliable interconnects

The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eliminate Cuor Cumigrations. In another aspect of the invention, a DC Voltage power supply is used to establish the negative bias.

Method for corrosion prevention during planarization

An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

Via electromigration improvement by changing the via bottom geometric profile

An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.

Structure and method to prevent charge damage from e-beam curing process

A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region of the ultra low-K dielectric layer, evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region, and removing the ultra low-K dielectric layer in the first region with a developer.

Semiconductor processing system with ultra low-K dielectric

A method of forming a barrier layer and cap comprised of CuSiN for an interconnect. We provide an interconnect opening in a dielectric layer over a semiconductor structure. We form a CuSiN barrier layer over the sidewalls and bottom of the interconnect opening by reacting with the first copper layer. We then form an interconnect over the CuSiN layer filling the interconnect opening. We can form a CuSiN cap layer on the top surface of the interconnect.

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

Growing community of inventors

Singapore, Singapore

Bei Chao Zhang