Rf Micro Devices, Inc.

Realtek Semiconductor Inc.

University of California

At+t Corp.

Applied Materials, Inc.

Lucent Technologies Inc.

At&t Bell Laboratories

Wionics Research

Resonext Communications, Inc.

Behzad Razavi

Pengfei Zhang

Han-Chang Kang

Lawrence Camest West

Zaw Soe

Bryan D Ackland

Turgut Sefket Aytur

Ran Yan

Chet Soorapanth

Tai-Cheng Lee

Jri Lee

A direct conversion ultrawideband transceiver employing three phase locked loops (PLLs). The PLLs are preferably fixed-frequency PLLs that operate continuously, at different frequencies, with a selected frequency determined by selecting the output of one of the three PLLs. The use of three PLLs is suitable for use in a communication system employing frequency hopping across three bands or sub-bands.

CMOS transceiver for communication system

A circuit including: an optical detector for detecting an optical pulse and generating therefrom a current pulse on an output; a pulse detector circuit having an input electrically connected to the optical detector and having an output for outputting a detection pulse in response to detecting the current pulse on its input, said pulse detector circuit including: a resettable amplifier including an input for receiving the current pulse from the optical detector, a reset terminal for resetting the amplifier after the amplifier detects the current pulse on its input, and an output for outputting a signal from which the detection pulse is derived; and a reset delay chain feeding back to the reset terminal of the resettable amplifier a feedback signal derived from the output signal of the resettable amplifier.

Pulse detector which employs a self-resetting pulse amplifier

The inventive technique can dynamically adjust the current being applied within the components of a prescaler or divider. This dynamic scaling of the current can improve the speed of the divider by a factor of two or reduce the average current in half when compared to the conventional prescaler. Inverters are used to directly adjust the dynamic value of the currents. The removal of the conventional NMOS device within the conventional circuit eliminates one gate delay in the CML prescaler. Second, the inventive prescaler circuits operate under a current injection/extraction technique. A group of small matched inverters can be used to drive each current switching circuit independently within the entire prescaler as compared to a large buffer driving the entire conventional prescaler. Finally, dynamic current scaling offers the designer additional flexibility in the design trade off between the maximum current applied to the load and achieving the maximum performance.

High-speed latching technique and application to frequency dividers

A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 &#x3bc;m CMOS technology.

High-speed clock and data recovery circuit

A high-speed latch includes a latch unit and a first current source. The latch unit has a first input terminal for receiving a first input signal and a first output terminal for outputting a first output signal. The first current source is coupled to the first output terminal, and is enabled for providing the first output terminal with a first driving current to reduce a voltage difference between the first output signal and the first input signal when the first output signal and the first input signal correspond to different logic states.

Data latch

A low noise amplifier (LNA) for filtering an input signal to generate an output signal. The low noise amplifier includes a switched loading circuit having a plurality of loading units, each of the loading units determining a corresponding center frequency of the low noise amplifier. The switched loading circuit selectively enables a loading unit having the desired corresponding center frequency. At least one converters coupled to the switched loading circuit converts a voltage of the input signal into a loading current and passes the loading current through the enabled loading unit to generate the output signal.

Low noise amplifier and related method

A mixer circuit of the present invention includes a gain stage configured to receive a first signal and a modulated bias current, and in accordance therewith, produce an output signal, the gain stage generating a first current and receiving the modulated bias current from a bias circuit on a common node. The bias circuit includes an input configured to receive a second signal, and in accordance therewith, generate the modulated bias current. The mixer circuit also includes a current shunt circuit for generating a second current. The first current, the second current, and the modulated bias current are coupled to the common node. In one embodiment, the first signal is approximately a square wave, and the frequency of the first signal is one-third the frequency of the second signal.

Low noise mixer circuit with improved gain

A stabilization technique that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay element, thereby obviating the need for resistors in the loop filter.

Stabilization technique for phase-locked frequency synthesizers

A local oscillator architecture provides a signal at an output frequency with reduced pulling effect. A voltage controlled oscillator (VCO) generates a first signal having a frequency that is a fraction of the output frequency. A frequency shifter generates a second signal with a frequency substantially equal to the difference between the VCO frequency and the output frequency. Single-sideband mixers are used to produce output signals at the sum of the VCO frequency and the shifted frequency while suppressing an unwanted sideband at the difference of the two frequencies.

Local oscillator architecture to reduce transmitter pulling effect and minimize unwanted sideband

In accordance with embodiments of the present invention, a receiver system is provided with a variable gain mixer circuit that is advantageous over current architectures used in wireless communication systems. The use of a variable gain mixer circuit simplifies the receiver architecture resulting in the elimination of additional circuit blocks and a reduction in complexity and cost. Moreover, one embodiment of the present invention includes a mixer circuit comprising a mixer core, a bias circuit coupled to the mixer core for providing a bias current, and a variable impedance network. The mixer core receives input signals and generates output currents that are coupled to the variable impedance network. Each of the output currents are selectively coupled to a voltage output node through a variable impedance. Variable gain is established by varying the impedance between the output currents of the mixer core and the voltage output node.

Variable gain mixer circuit

In accordance with the present invention a mixer circuit noise reduction technique is provided. The mixer circuit of the present invention includes a gain stage for receiving a first signal and producing an output signal. The mixer circuit also includes a bias circuit coupled to the gain stage through a common node for providing a bias current to the gain stage, the bias circuit having an input for receiving a second signal, and in accordance therewith, varying the bias current. Additionally, the mixer circuit includes a frequency dependent current shunt circuit coupled between the common node and a reference voltage, wherein a first portion of the bias current frequency components within a first frequency range are coupled to the reference voltage by the shunt circuit, and a second portion of the bias current frequency components within a second frequency range are coupled to the reference voltage by the shunt circuit, the first portion being larger than the second portion. As a result, the noise in the mixer circuit is reduced while the gain is enhanced.

Mixer noise reduction technique

A method and apparatus of converting differential signals to single-ended signals. The method includes receiving a differential signal comprising a first current and a second current and applying the second current to a first load to generate a first voltage. A third current is generated in response to the first voltage. The first current is summed with the third current and applied to a second load to generate the single-ended signal.

Differential to single-ended converter with large output swing

Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.

Method and apparatus for reducing DC offset

A low noise amplifier (LNA)/mixer/frequency synthesizer circuit for the front end of a RF system. The LNA/mixer/frequency synthesizer circuit is fabricated as an integrated circuit utilizing 0.6 .mu.M CMOS technologies. The LNA within the circuit is provided a bias current from a power supply. Due to the CMOS construction of the LNA, a significant amount of unused power is available within the LNA. The frequency synthesizer requires the same bias current as does the LNA. The frequency synthesizer is directly coupled to the LNA, wherein the unused bias current of the LNA is used to supply the required bias current to the oscillators within the frequency synthesizer. Since the bias current used by the frequency synthesizer is drawn from the surplus of the LNA, a RF system front end is provided that has greatly reduced power requirements. The LNA is coupled to the frequency synthesizer, via an inductor. The inductor provides resonance to a node between the LNA and the frequency synthesizer that joins to the mixer. The inductor suppresses band harmonics while preserving the unused bias current.

Low noise amplifier/mixer/frequency synthesizer circuit for an RF system

A sample-and-hold circuit is formed in bipolar transistor technology with the aid of clocked and complementary-clocked bipolar transistors in combination with a holding capacitor whose output terminal, in going from sample to hold phases of the clock, undergoes change in voltage .DELTA.V equal to the input voltage samples Vin applied to its input terminal during the sample phases (electrical bootstrapping operation). In particular, an input terminal of the holding capacitor is connected to a clocked input voltage device that ensures that, during the sample phases, the input voltage applied to the input terminal of the capacitor represents the input voltage being sampled, and that during the hold phases of the clock, the input terminal of the capacitor is electrically clamped. An output terminal of the holding capacitor is connected to one of the clocked transistors and to an auxiliary bipolar transistor whose base terminal is controlled by a complementary-clocked voltage-dropping device. This complementary-clocked voltage-dropping device sets the output terminal of the capacitor to a fixed voltage during the sample phases and is disconnected from this output terminal during the hold phases, whereby during the hold phases the output terminal of the holding capacitor is electrically floating and the voltage thereat represents the input voltage during the immediately preceding sample phase.

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Los Angeles, CA, United States of America

Behzad Razavi