Space Exploration Technologies Corp.

Broadcom Corporation

Behzad Nourani

Masoud Kahrizi

Alireza Mehrnia

Bagher Afshar

Bernd Pregardier

Alex Ahmad Mirzaei

Ali Sajjadi

Babak Vakili-Amini

Alireza Tarighat Mehrabani

In an embodiment, an apparatus includes a first digital beamformer (DBF) associated with a first subset of antennas of a phased array antenna, the first DBF including a transmit section associated with transmission of a first signal at a first frequency in a transmit mode and a receive section associated with receiving of a second signal at a second frequency in a receive mode, the second frequency being different from the first frequency. The apparatus includes a second DBF associated with a second subset of antennas of the phased array antenna. The first and second DBFs are configured to receive a local oscillator signal having the first frequency from a common local oscillator in the transmit mode and receive the local oscillator signal having the second frequency from the common local oscillator in the receive mode.

Half duplex mode digital beamforming device

In an embodiment, a device is included in a communications system, the device including a plurality of antenna elements configured in a phased array antenna; a plurality of integrated circuit (IC) chips, wherein each IC chip of the plurality of IC chips is associated with a respective subset of antenna elements of the plurality of antenna elements, and wherein, for each IC chip of the plurality of IC chips, the associated subset of antenna elements is used for transmitting and receiving radio frequency (RF) signals by the IC chip; and a local oscillator configured to generate a common local oscillator signal and provide the common local oscillator signal to each IC chip of the plurality of IC chips.

Methods, systems, and apparatuses are described for compensating for an undesired fractional spur due to a PLL in a communication system. The communication system includes a time-to-digital converter (TDC) that is configured to execute in parallel to the PLL. The TDC is configured to determine a phase difference between a reference frequency and an output oscillation signal provided by the PLL. The phase difference is received by a processor to estimate particular characteristics of the undesired fractional spur, and the estimate of the characteristics is used to construct an estimate of the undesired fractional spur.

Time-to-digital convertor-assisted phase-locked loop spur mitigation

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Irvine, CA, United States of America

Behzad Nourani