Motorola Corporation

Behrooz L Abdi

John E Hanna

Gary L Stuhlmiller

David M Gonzalez

Alex Wayne Hietala

Eric Main

Byron Bynum

Prior art differential track and hold amplifiers produce an error voltage when transitioning from a track mode to a hold mode. An error voltage limits the resolution of a track and hold amplifier. A first circuit (44) and a second circuit (45) couple a differential voltage to the storage capacitor. Control signals applied to the first and second circuits (44, 45) generate parasitic currents through parasitic capacitances which couple to a storage capacitor of a track and hold amplifier (41). The control signals applied to the first and second circuits (44, 45) are forced to transition an equal voltage magnitude to produce identical parasitic currents through the parasitic capacitance. Identical parasitic currents affect common mode voltage but do not change the differential voltage stored on the storage capacitor. A clamping circuit (50) clamps the voltage transition of the control signals to produce identical voltage transitions.

Circuit and method for reducing distortion in a track and hold amplifier

A communication device (100) employs a local oscillator (104) having an improved charge pump circuit (122). The charge pump circuit (122) has current mirrors (204, 208) in which a first transistor (224, 270) is biased to provide a substantially constant current. A resistor (226, 272) selectively conducts a reference current to bias a mirror transistor (228, 274). The current mirror (204, 208) provides improved dynamic performance thereby reducing global phase error of the communication device (100).

Switching current mirror for a phase locked loop frequency synthesizer

A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Differential high speed track and hold amplifier

A current switch circuit for operating with low supply voltages while not compromising dynamic range has been provided. The current switch circuit includes a differential pair of transistors having first (12) and second (20) transistors. The base of the first transistor is coupled to a bias voltage (V.sub.B) while its collector is coupled to an output (14) of the current switch circuit. The collector of the second transistor is coupled to a first supply voltage terminal while the base of the second transistor is coupled to a variable bias circuit (22) for alternately swinging the voltage applied to the base of the second transistor above or below the bias voltage applied to the base of the first transistor. When the voltage applied to the base of the second transistor is greater than the bias voltage applied to the base of the first transistor, a predetermined current is sunk from the output of the current switch. Otherwise, substantially zero current flows at the output of the current switch.

Low voltage precision switch

A pulse detector keeps track of the peak value of an analog input signal and clocks output data pulses into a flipflop and shift register at peak values thereof while it monotonically increases in magnitude for each polarity. The data input to the flipflop becomes logic zero once the analog input signal changes direction toward the opposite polarity, whereby the last output data pulse in the shift register corresponds to the maximum peak of the analog input signal during the given polarity.

Monotonic pulse detector

An offset cancellation circuit corrects DC offset appearing at the input of a comparator circuit. The first input of a summing junction receives an input signal containing DC offset. The output of the summing junction drives the input of the comparator and a feedback amplifier, the latter of which returns to the second input of the summing junction. Any DC offset is processed through the feedback amplifier where it subtracts from the input signal for providing zero DC offset at the input of the comparator.

Offset cancellation circuit and method of reducing pulse pairing

A frequency discriminator circuit is provided having increased resolution for detecting the frequency of a data input signal above and below a predetermined frequency threshold by monitoring a count value. The output signal of the frequency discriminator circuit remains at a first logic state provided the count value is reset by the data input signal before reaching a predetermined count value signifying that the frequency of data input signal is above the predetermined frequency threshold. The output signal of the frequency discriminator circuit switches to a second logic state if the count value reaches the predetermined count value before receiving a reset signal thereby indicating that the frequency of data input signal is below the predetermined frequency threshold.

Digital timing discriminator

A comparator having programmable hysteresis is provided. The signal supplied to an inverting input of the comparator (18) is determined by the logic state of the output of comparator and is a programmable factor of one of two predetermined signals (V.sub.REF1 or V.sub.REF2). The programmable factor is determined by the logic states of a plurality of control signals and can be adjusted by varying the logic states of the plurality of control signals.

Programmable hysteresis comparator

A peak detector circuit includes a switch for charging and discharging a capacitor at predetermined rates. In a first mode of operation, the switch is open and the peak detector functions to provide an output voltage that is indicative of the peak voltage level occurring at its input by charging a capacitor at a first predetermined rate. In a second mode of operation, the switch is closed and the peak detector functions to discharge the capacitor at a second predetermined rate and to a predetermined voltage. Subsequently in the second mode of operation, the peak detector then functions to provide an output voltage that follows its input voltage.

Switched peak detector

A deglitch circuit for suppressing transient signals that appear at an output node includes a bias circuit for providing a bias signal; a transistor having its collector-emitter conduction path coupled in series to the output node and having a base coupled to the bias signal; and a capacitive element coupled between the output node and the base of the transistor for rendering the transistor conductive in response to a transient signal such that a low impedance circuit path is presented to the transient signal.

Low power transient suppressor circuit

A peak detector circuit that provides a signal at an output terminal which represents the most positive peak voltage level applied at an input terminal. Comparator circuit is coupled to the input terminal and to the output terminal to determine which voltage signal thereof is more positive to provide an output current whenever the supplied input voltage exceeds the voltage at the output terminal. The output current is then amplified for providing a current to a capacitor circuit for developing a voltage across the capacitor equal to the positive peak voltage level applied at the input terminal. A buffer circuit coupled to the capacitor circuit transforms the voltage across capacitor circuit to the output terminal and includes a clamping circuit for clamping coupled between the output terminal and the comparator circuit to prevent the comparator circuit output from saturating whenever the voltage applied at the input terminal is less than that appearing at the output terminal.

Low power peak detector/buffer with fast charge-up time

A current mirror provides an output current that is scaled in magnitude with respect to an applied input current includes first and second current turnaround circuits and circuitry coupled between the two current turnaround circuits which is responsive to the first current turnaround circuit for sourcing a current to the second current turnaround circuit the magnitude of which is scaled with respect to the input current that is sourced to the first current turn around circuit.

Current mirror have large current scaling factor

A voltage to absolute value current converter circuit provides an output current signal which is proportional to the absolute value of the AC portion of an input voltage signal. This conversion is accomplished without the use of a capacitor which allows the circuit to be implemented in integrated circuit form.

Voltage to absolute value current converter

A current mode logic gate for logically combining input logic signals is comprised of a first pair of transistors each having a base, collector and at least one emitter with the emitters being coupled together to a current source while the bases are respectively coupled to first and second inputs of the gate. At least one other pair of transistors are provided the bases of which are coupled to third and fourth inputs of the gate while the collectors are respectively coupled to first and second outputs of the gate. Each of the transistors of the other pair have first and second emitters with the first emitters being coupled to the collector of one of the transistors of the first pair of transistors while the second emitter of one of the transistors of the other pair is coupled to the collector of the other one of the first pair of transistors. The second emitter of the other one of the other pair of transistors is either left open-circuited or is shorted to its base. The collectors of the other pair of transistors are respectively coupled to first and second outputs of the gate.

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Chandler, AZ, United States of America

Behrooz L Abdi