Qualcomm Incorporated

University of Notre Dame Du Lac

Behnam Sedighi

Dongwon Seo

Nitz Saputra

Shahin Mehdizad Taleie

Ashok Swaminathan

Bhushan Shanti Asuri

Honghao Ji

Michael Niemier

Joseph J Nahas

Elias Dagher

Andrew Weil

Ibrahim Ramez Chamas

Xiaobo Sharon Hu

Sang Min Lee

Xilin Liu

Tao Luo

Igor Gutman

Jeremy Darren Dunworth

Shrenik Patel

Dinesh Jagannath Alladi

Sang-June Park

Vinod Panikkath

Liang Dai

Lei Sun

Krishnaswamy Thiagarajan

Ayush Mittal

Kentaro Yamamoto

Sameer Vasantlal Vora

Parisa Mahmoudidaryan

Aram Akhavan

Zhilong Tang

Negar Rashidi

Ping Wing Lai

Tonmoy Biswas

Jaswinder Singh

Siyu Yang

Eunyung Sung

Chen Jiang

Vinay Kundur

Wei Guo

Indranil Palit

X Sharon Hu

Shi Bu

Tszwing Choi

Henry Lau

Sudharsan Kanagaraj

Yen-Wei Chang

Sy-Chyuan Hwu

A capacitor device comprises a semiconductor substrate with multiple metal layers above the substrate. a first metal layer has a first plurality of bottom terminals elongated in a first direction, and a first plurality of top terminals, electrically coupled to each other, elongated in the first direction and interleaved with the first plurality of bottom terminals. A second metal layer between the semiconductor substrate and the first metal layer has a second plurality of bottom terminals elongated in the first direction, and a second plurality of top terminals, electrically coupled to each other and the first plurality of top terminals, elongated in the first direction and interleaved with the second plurality of bottom terminals.

Matching unit capacitor with multiple metal layers

Techniques and apparatus for reducing sensitivity (e.g., less gain variation due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes a pair of differential input transistors, a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier, a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, and a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes.

Dynamic amplifier with reduced sensitivity

Techniques and apparatus for successive approximation register (SAR) analog-to-digital converters (ADCs) with variable resolution. One example SAR ADC is generally configured to convert an analog input signal to a digital output signal, wherein a quantization size of a least significant bit (LSB) associated with the digital output signal is configured to depend on an amplitude of the analog input signal. By utilizing the techniques and apparatus described herein, a SAR ADC may be capable of a higher maximum sampling rate or a lower power dissipation.

Successive approximation register (SAR) analog- to-digital converter (ADC) with input-dependent least significant bit (LSB) size

Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.

Alias rejection in analog-to-digital converters (ADCs)

Methods and apparatus for noise shaping in multi-stage analog-to-digital converters (ADCs). An example ADC generally includes a first conversion stage having a residue output; an amplifier having an input selectively coupled to the residue output of the first conversion stage; a second conversion stage having an input selectively coupled to an output of the amplifier; and a switched-capacitor network having a first port coupled to the input of the amplifier and having a second port coupled to the input of the second conversion stage, the switched-capacitor network being configured to provide a second-order or higher noise transfer function for noise shaping of quantization noise of the second conversion stage.

Noise shaping in multi-stage analog-to-digital converters

Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

Dynamic range adjustment for analog-to-digital converter (ADC)

Methods and apparatus for adaptively generating a reference voltage (V) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a Vgeneration circuit coupled to the regulation circuit and configured to adaptively generate a Vfor the regulation circuit.

Adaptive switch biasing scheme for digital-to-analog converter (DAC) performance enhancement

A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV) coupled to the first inverter (INV), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV) coupled to the second inverter (INV), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop

A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.

Apparatus and method for measuring current source mismatches in current-steering DAC by re-using R2R network

An RF-DAC transmitter is provided that includes an in-phase channel, a quadrature-phase channel, a first intermediate-phase channel, and a second intermediate-phase channel. Each channel includes a pair of interleaved RF-DACs for producing a pair of interleaved RF signals and a subtractor.

Digital RF-DAC

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.

Digital-to-analog converter (DAC) with mixing-mode parallel path image attenuation

An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

Image calibration for time-interleaved digital-to-analog converter

A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

Communication circuit including a transmitter

The present disclosure describes aspects of segmented resistor architecture for digital-to-analog converters (DACs). In some aspects, a DAC circuit is implemented with a first resistor network coupled to a set of binary code-controlled current sources and a second resistor network that includes a resistor coupled between the first resistor network and an output of the DAC circuit. A set of thermometer code-controlled current sources are coupled to a node of the second resistor network and provide varying amounts of current. This current is scaled based on a resistance of the second resistor network's resistor, which is higher than a resistance of the first resistor network and effective to increase a combined output impedance of the first and second resistor networks. The increase of output impedance reduces noise of the resistor networks that transfers to the output of the DAC circuit, thereby improving signal-to-noise performance of the DAC circuit.

Segmented resistor architecture for digital-to-analog converters

A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.

Low voltage input calibrating digital to analog converter

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La Jolla, CA, United States of America

Behnam Sedighi