Silanna Asia Pte Ltd

Psemi Corporation

Peregrine Semiconductor Corporation

Silannapte Ltd

Befruz Tasbas

Stuart B Molin

Shanghui Larry Tu

Raymond Jiang

Michael Andrew Stuber

Simon Edward Willard

Sinan Goktepeli

Alain Duvallet

Michael A Stuber

A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.

Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact

Systems, methods, and apparatus for an improved protection from charge injection into layers of a device using resistive structures are described. Such resistive structures, named s-contacts, can be made using simpler fabrication methods and less fabrication steps. In a case of metal-oxide-semiconductor (MOS) field effect transistors (FETs), s-contacts can be made with direct connection, or resistive connection, to all regions of the transistors, including the source region, the drain region and the gate.

S-contact for SOI

A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.

Integrated circuit connection arrangement for minimizing crosstalk

A semiconductor package includes a leadframe having perimeter package leads and electrical connectors, a single semiconductor die having a back-side electrical contact and front-side electrical contacts, an electrically conductive clip ('clip'), and a top semiconductor die having a frontside and a backside. The single semiconductor die includes two or more transistors. Two or more of the front-side electrical contacts of the semiconductor die are electrically coupled to and physically mounted to respective electrical contacts of the leadframe. An electrical contact surface of the clip is electrically coupled to and physically mounted to an electrical connector of the leadframe. Another electrical contact surface of the clip is physically mounted to and electrically coupled to the back-side electrical contact of the semiconductor die. The backside of the top semiconductor die is physically mounted to yet another surface of the electrically conductive clip.

Leadframe and integrated circuit connection arrangement

In an active layer over a semiconductor substrate, a semiconductor device has a first lateral diffusion field effect transistor (LDFET) that includes a source, a drain, and a gate, and a second LDFET that includes a source, a drain, and a gate. The source of the first LDFET and the drain of the second LDFET are electrically connected to a common node. A first front-side contact and a second front-side contact are formed over the active layer, and a substrate contact electrically connected to the semiconductor substrate is formed. Each of the first front-side contact, the second front-side contact, and the substrate contact is electrically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.

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San Diego, CA, United States of America

Befruz Tasbas