International Business Machines Corporation

Beeman Noel Fallwell, Jr

John Howard Barker

William Brooks Ott

Matt A Kaltenbach

A technique and mechanism for reducing memory latency asymmetry in a multiprocessor system by replacing one (or more) processors with a bypass or pass-through device. Using the pass-through mechanism, the reduced number of processors in the system enables all of the remaining processors to connect to each other directly using the interconnect links. The reduction in processor count improves symmetry and reduces overall latency thereby potentially improving performance of certain applications despite having fewer processors. In one specific implementation, the pass through device is used to connect two HyperTransport links together where each of the links is connected to a processor at the other end.

Pass through circuit for reduced memory latency in a multiprocessor system

In a local area network for data communications, stations which distributively control their access to a common bus or other medium are able to identify the location of any 'hot' station transmitter (one stuck continuously in an 'on' condition which cannot be isolated from the medium). Such networks are effectively disabled by a hot carrier, since each station conditions its access on sensing the medium as previously idle. The present 'loop test' method permits all stations in the network to quickly establish the location of a hot transmitter, and thereby quickly direct field repair personnel to that location. It also permits operators to take action to physically disconnect the faulty transmitter from the medium, so that the other stations may continue to use the network until the fault is repaired.

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Cary, NC, United States of America

Beeman Noel Fallwell, Jr