California Institute of Technology

Fotonation Cayman Limited

The United States of America As Represented by the Administrator of the

United States of America As Represented by the Administrator of Nasa

Sandia Corporation

Fotonation Limited

Pelican Imaging Corporation

Bedabrata Pain

Eric R Fossum

Thomas J Cunningham

Guang Yang

Zhimin Zhou

Bruce R Hancock

Orly Yadid-Pecht

Chao Sun

Kartik Venkataraman

Dan C Lelescu

Xinyu Zheng

Robert H Nixon

Barmak Mansoorian

Shouleh Nikzad

Suresh Seshadri

Monico Ortiz

Chris Wrigley

Shree Kumar Nayar

Jacques Duparre

Andrew Kenneth John McMahon

Paul Gallagher

Sunetra K Mendis

George A Soli

Brad Minch

Timothy J Shaw

Brita H Olson

Junichi Nakamura

Roger Panicacci

Michael E Hoenk

Sabrina Elizabeth Kemeny

Todd J Jones

Martin Agan

Colin L Smithpeter

Matthew R Dickie

Robert O Nellums

Kenneth W Newton

Christopher James Wrigley

Eddie R Hoover

Julie B Heynssens

Bob H Nixon

Zhimim Zhou

Chris Pasqualino

Ed H Satorius

Tim J Shaw

Gary L Stevens

Greg Bearman

Michael J Pelletier

Imager arrays, array camera modules, and array cameras in accordance with embodiments of the invention utilize pixel apertures to control the amount of aliasing present in captured images of a scene. One embodiment includes a plurality of focal planes, control circuitry configured to control the capture of image information by the pixels within the focal planes, and sampling circuitry configured to convert pixel outputs into digital pixel data. In addition, the pixels in the plurality of focal planes include a pixel stack including a microlens and an active area, where light incident on the surface of the microlens is focused onto the active area by the microlens and the active area samples the incident light to capture image information, and the pixel stack defines a pixel area and includes a pixel aperture, where the size of the pixel apertures is smaller than the pixel area.

Systems and methods for controlling aliasing in images captured by an array camera for use in super resolution processing using pixel apertures

Systems and methods in accordance with embodiments of the invention implement modular array cameras using sub-array modules. In one embodiment, an X&#xd7;Y sub-array module includes: an X&#xd7;Y arrangement of focal planes, where X and Y are each greater than or equal to 1; and an X&#xd7;Y arrangement of lens stacks, the X&#xd7;Y arrangement of lens stacks being disposed relative to the X&#xd7;Y arrangement of focal planes so as to form an X&#xd7;Y arrangement of cameras, where each lens stack has a field of view that is shifted with respect to the field-of-views of each other lens stack so that each shift includes a sub-pixel shifted view of the scene; and image data output circuitry that is configured to output image data from the X&#xd7;Y sub-array module that can be aggregated with image data from other sub-array modules so that an image of the scene can be constructed.

Thin form factor computational array cameras and modular array cameras

Pixels, imagers and related fabrication methods are described. The described methods result in cross-talk reduction in imagers and related devices by generating depletion regions. The devices can also be used with electronic circuits for imaging applications.

Pixels, imagers and related fabrication methods

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Sparsely-bonded CMOS hybrid imager

An apparatus and associated method are provided. A first silicon layer having at least one of an associated passivation layer and barrier is included. Also included is a composite anti-reflection layer including a stack of layers each with a different thickness and refractive index. Such composite anti-reflection layer is disposed adjacent to the first silicon layer.

Apparatus and method of manufacture for depositing a composite anti-reflection layer on a silicon surface

For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.

Analog bus driver and multiplexer

An imager apparatus and associated starting material are provided. In one embodiment, an imager is provided including a silicon layer of a first conductivity type acting as a junction anode. Such silicon layer is adapted to convert light to photoelectrons. Also included is a semiconductor well of a second conductivity type formed in the silicon layer for acting as a junction cathode. Still yet, a barrier is formed adjacent to the semiconductor well. In another embodiment, a starting material is provided including a first silicon layer and an oxide layer disposed adjacent to the first silicon layer. Also included is a second silicon layer disposed adjacent to the oxide layer opposite the first silicon layer. Such second silicon layer is further equipped with an associated passivation layer and/or barrier.

Apparatus and method of manufacture for an imager equipped with a cross-talk barrier

A miniaturized camera which is programmable and provides low power consumption. An active pixel image sensor used in the highly miniaturized camera provides improved imaging functionality as well as reduced power consumption, extending the possible life time of the camera system. The spread spectrum nature of transmission and reception improves data integrity as well as data security. The ability of the highly miniaturized wireless camera to receive commands as well as transmit image data provides improved functionality and a variable rate of power consumption to be set according to the application and needs of the situation.

Highly miniaturized, battery operated, digital wireless camera using programmable single chip active pixel sensor (APS) digital camera chip

A photoelectronic device and an avalanche self-quenching process for a photoelectronic device are described. The photoelectronic device comprises a nanoscale semiconductor multiplication region and a nanoscale doped semiconductor quenching structure including a depletion region and an undepletion region. The photoelectronic device can act as a single photon detector or a single carrier multiplier. The avalanche self-quenching process allows electrical field reduction in the multiplication region by movement of the multiplication carriers, thus quenching the avalanche.

Single photon detection with self-quenching multiplication

An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed.

Nano-multiplication region avalanche photodiodes and arrays

Methods for bringing or exposing metal pads or traces to the backside of a backside-illuminated imager allow the pads or traces to reside on the illumination side for electrical connection. These methods provide a solution to a key packaging problem for backside thinned imagers. The methods also provide alignment marks for integrating color filters and microlenses to the imager pixels residing on the frontside of the wafer, enabling high performance multispectral and high sensitivity imagers, including those with extremely small pixel pitch. In addition, the methods incorporate a passivation layer for protection of devices against external contamination, and allow interface trap density reduction via thermal annealing. Backside-illuminated imagers with illumination side electrical connections are also disclosed.

Back-illuminated imager and method for making electrical and optical connections to same

The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.

Photodiode CMOS imager with column-feedback soft-reset for imaging under ultra-low illumination and with high dynamic range

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Los Angeles, CA, United States of America

Bedabrata Pain