International Business Machines Corporation

Bechara Fouad Boury

Terence Joseph Lohman

Richard Gerard Hofmann

Nader Amini

Kenichi Tsuchiya

Paul Michael Steinmetz

Michael B Mitchell

Sherwood Brannon

Richard Louis Horne

Patrick Maurice Bland

A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

Computing device with asynchronous auxiliary execution unit

A computer system and method allow memory locations in both system memory and expansion memory devices coupled to an input/output (I/O) bus to be cacheable in a central processing unit (CPU) cache. The computer system contains an I/O bus connected to I/O devices and an expansion bus connected to expansion memory devices, a system memory not accessible via the I/O bus or expansion bus, and the system bus used for conducting data transfers between the I/O bus and both the CPU cache and system memory. The I/O bus supports data transfers between pairs of I/O devices, and I/O devices and expansion memory devices on the expansion bus, as well as data transfers between individual I/O devices and the system, which presents a problem of maintaining coherency in the CPU cache when data is written by one I/O device or expansion memory device to a cacheable memory location in another I/O device or expansion memory device. The computer system employs a snoop/data invalidation function at the system interface to the I/O bus to determine when a memory location in an expansion memory device coupled to the expansion bus is being written to by another expansion memory device coupled to the expansion bus or an I/O device coupled to the I/O bus. If such a write is taking place, it is then determined if the address of the location being written is in and address range predesignated as cacheable; if so, then the CPU cache controller or other device controlling the CPU cache is notified that memory at a cacheable location in an expansion memory device has been overwritten.

Computer system and method for snooping date writes to cacheable memory

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Raleigh, NC, United States of America

Bechara Fouad Boury