Samsung Electronics Co., Ltd.

Beak Hyung Cho

Kwang Jin Lee

Joon Min Park

Young Don Choi

Qi Wang

Jong Pil Son

Du Eung Kim

Ki Whan Song

Yu Hwan Ro

A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

Voltage control method to minimize a coupling noise between adjacent global bit lines during read-while operation and memory device using the same

In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

Semiconductor device having memory array, method of writing, and systems associated therewith

A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line. In a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, so that data writing time is reduced under the same conditions as a normal write mode.

Semiconductor memory devices having core structures for multi-writing

The invention discloses a semiconductor memory device in which faulty cells causing standby current failure will be replaced with redundancy cells. The semiconductor memory device includes: a plurality of word lines, a plurality of bit lines, a plurality of cells connected between the word lines and bit lines for storing data and a memory cell array of a plurality of cell blocks having a plurality of cell power lines for providing supply voltage to the cells; a plurality of row decoder circuits for decoding external row addresses and generating selection signals for predetermined word lines included in the cell blocks; and a plurality of cell power repairing circuits for selectively blocking between cell power lines providing supply voltage to faulty cells and power source at an occurrence of faulty cells causing standby current failure. At this time, the cell power lines of the cell blocks are arranged in an identical direction to word lines; the row decoder circuits are respectively arranged between two neighboring cell blocks; and the cell power repairing circuits are respectively arranged between the cell blocks of the memory cell array, thereby reducing the size of a chip.

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Hwaseong-si, South Korea

Beak Hyung Cho