Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Bazhong Shen

Mehmet Vakif Tazebay

Peiqing Wang

Ahmad Chini

Chung Ming Tu

Yencheng Chen

Mark Kent

Erik Richard Stauffer

Avi Kliger

Yitshak Ohana

Payam Torab Jahromi

Anatoli Shindler

Tak (Tony) Lee

A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor. The at least one processor may be configured to transmit a first synchronization sequence to a secondary device, detect a second synchronization sequence transmitted by the secondary device, the second synchronization sequence differing from the first synchronization sequence, and after detection of the second synchronization sequence, initiate a training stage, the train stage comprising exchanging training frames with the secondary device. The at least one processor may be further configured to enter a data mode for data transmissions after completion of the training stage, the data transmissions being distinct from the training frames. In the data mode, data may be forward error correction encoded and then scrambled.

Transition timing and training stage operation

A system of codeword puncturing for varying code rates may include at least one transmitter circuit. The at least one transmitter circuit may be configured to perform error correction coding to generate codewords at a first code rate. The at least one transmitter circuit may be further configured to puncture a number of bits from a location within each of the codewords to implement a second code rate that is greater than the first code rate. The at least one transmitter circuit may be further configured to provide the punctured codewords for transmission. The device may further include at least one receiver circuit that may be configured to receive bit sequences comprising received punctured codewords. The at least one receiver circuit may be further configured to insert bits into the bit sequences to compensate for the puncturing and perform error correction decoding on the bit sequences including the inserted bits.

Codeword puncturing for varying code rates

Synchronization and training stage operation

A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

The present disclosure is directed to a system and method for detecting burst noise. The system and method are described in the exemplary context of a cable modem system and can be used in such a system to specifically detect upstream burst noise. Once detected, the system and method can adjust the upstream receiver that receives data corrupted by the upstream burst noise to reduce the potentially deleterious effects that the burst noise can have on, for example, the packet error rate and/or data rate of the upstream receiver.

Upstream burst noise detection

The present disclosure is directed to a system and method for encoding k input symbols, using a Reed-Solomon erasure correction code, into a longer stream of n output symbols for transmission over an erasure channel. The present disclosure is further directed to a system and method for recovering the original k input symbols from only (and any) k output symbols (out of the n output symbols) received over the erasure channel. A symbol is a generic data unit consisting of one or more bits that can be, for example, a packet. The systems and methods of the present disclosure provide for an adjustable code rate that can be readily adapted based on changing channel conditions without having to reconstruct the encoder/decoder. As a result, such an encoder/decoder can be referred to as rate-independent.

Systematic rate-independent Reed-Solomon erasure codes

Aspects of a method and system for determining a limited soft buffer size on transport blocks for rate matching are provided. A data stream may be processed for transmission between a base station (eNodeB) and a UE via HARQ procedures. A two-stage rate-matching algorithm may be used in the HARQ procedures. A limited virtual soft buffer size at the UE in the two-stage rate-matching algorithm may be calculated on site based on channel condition information, available channel bandwidth, number of layers in spatial multiplexing, and the capacity of the UE, respectively. The data stream may be first rate-matched to the calculated limited soft buffer size available at the UE, and forwarded for second stage rate-matching to an actual physical channel size determined by the base station. The amount of bits forwarded for second stage rate-matching may equal to the calculated limited virtual soft buffer size of the virtual soft buffer.

Method and system for determining limited soft buffer size on transport blocks for rate matching

Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.

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Irvine, CA, United States of America

Bazhong Shen