Taiwan Semiconductor Manufacturing Comp. Ltd.

Grand Plastic Technology Corporation Taiwan

Baw-Ching Perng

Hun-Jan Tao

Chia-Hui Lin

Cheng-Chung Lin

Ai-Sen Liu

Ming-Ta Lei

Peng-Fu Hsu

Ju-Wang Hsu

Yih-Shung Lin

Bor-Wen Chan

Wen-Kai Wan

Jyu-Horng Shieh

Hsien-Kuang Chiu

Chih-Hsin Ko

Ming-Huan Tsai

Yuan-Hung Chiu

Kuei-Wu Huang

Chih-Cheng Wang

Yi-Chun Huang

Yih-Hsiung Lin

Wen-Chih Chiou

Syun-Ming Jang Jang

Fu-Liang Yang

Chia-Jen Chen

Chun-Chieh Lin

Yi-Nien Su

Ying-Tsung Chen

Hao-Yu Chen

Fang-Cheng Chen

Bing-Yue Tsui

Yi-Chen Huang

Jang-Shiang Tsai

Lawrence Chiang Sheu

Mei-Hui Sung

Jun-Lung Huang

Hsin-Ching Shih

Lawrance Hsu

Hsieh Yue Ho

Hsiao Shih-Yi

Kang Tsung-Kuei

Chih-Feng Huang

Jann-Shyang Liang

Yue-Ho Hsieh

Shih-Yi Hsiao

Ming-Dai Lei

Yaun-Hung Chiu

Ming-Huang Tsai

Ming-Huan Tsei

Bow-Wen Chan

Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

Surface treatment of metal interconnect lines

A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.

Measuring low dielectric constant film properties during processing

A semiconductor structure includes a substrate, and a first MOS device on the first region of the substrate wherein the first MOS device includes a first spacer liner. The semiconductor structure further includes a second MOS device on the second region wherein the second MOS device includes a second spacer liner. A first stressed film having a first thickness is formed over the first MOS device and directly on the first spacer liner. A second stressed film having a second thickness is formed over the second MOS device and directly on the second spacer liner. The first and the second stressed films may be formed of a same material.

CMOS devices with improved gap-filling

A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width win the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H/Nand SOchemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width wby a HBr/O/Clplasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O/Clchemistry. The underlayer is stripped by an Oashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w&#x2212;w) is possible than in prior art methods.

Method of trimming technology

A Cu damascene structure is formed where Cu diffusion barrier is formed by treating the top surface of the surrounding low-k interlayer dielectric with nitrogen or carbon containing medium to form a silicon nitride or silicon carbide diffusion barrier rather than capping the top surface of the Cu with metal diffusion barrier as is conventionally done.

Surface treated low-k dielectric as diffusion barrier for copper metallization

In a method of forming a double gate device, a buried insulating layer having a thickness of less than about 30 nm is formed on a first substrate. A second substrate is formed on the buried insulating layer. A pad layer is formed over the second substrate. A mask layer is formed over the pad layer. A first trench is formed extending through the pad layer, second substrate, buried insulating layer and into the first substrate. The first trench is filled with a first isolation. A second trench is formed in the first isolation and filled with a conductive material. An MOS transistor is formed on the second substrate. A bottom gate is formed under the buried insulating layer and self-aligned to the top gate formed on the second substrate.

Self-aligned double gate device and method for forming same

Methods and structures for critical dimension or profile measurement are disclosed. The method provides a substrate having periodic openings therein. Material layers are formed in the openings, substantially planarizing a surface of the substrate. A scattering method is applied to the substrate with the material layers for critical dimension (CD) or profile measurement.

Methods and structures for critical dimension and profile measurement

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Method for multiple spacer width control

A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

Recessed polysilicon gate structure for a strained silicon MOSFET device

A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

Process for patterning high-k dielectric material

A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes COand ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

Process for removing organic materials during formation of a metal interconnect

The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact. Another form of the electrode structure of the present invention is making both the positive and negative electrodes on the front side of the LED by etching the p-type semiconductor of the pn junction and forming a strip of negative electrode on the n-type semiconductor, the positive electrode is formed on the p-type semiconductor.

Method for wet etching of high k thin film at low temperature

A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

Method and structure for ultra narrow gate

A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

Method for forming multiple spacer widths

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Hsin-Chu, Taiwan

Baw-Ching Perng