Compaq Computer Corporation, Inc.

Other

Bassam N Elkhoury

Brian S Hausauer

Miguel A Perez

Scott T McFarland

Dwight D Riley

Christopher J Pettey

Thomas R Seeman

Robert S Wright

Alexander C Ekrot

Russell J Wunderlich

Kris P Dehnel

In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an operation to save data in memory is performed. Thereafter, the interrupted processor-to-bus cycle is resumed.

Memory coherency in a processor-to-bus cycle in a multi-processor system

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-EISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches the bridge interface from the bridge or PCI bus, and it is recognized that the address is within the range, then the fast burst mode is allowed, and write addresses are allowed to follow one another without the delay for the snoop phase or the possibility of defer or retry.

Bus-to-bus bridge in computer system, with fast burst memory range

In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of the memory access cycle, a snoop routine is initiated with respect to the memory address. The memory access cycle is continued without awaiting responses from another one of the processors if a second one of the processors provides a signal which indicates that immediate completion of the memory access cycle will not disturb the integrity of data stored in the system.

Performing a memory access cycle in a multi-processor computer system

A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, preferably of the PCI type in the example embodiment. A host-to-PCI bridge is used for coupling the processor bus to the expansion bus. Other buses may be coupled to the PCI bus via PCI-to-(E) ISA bridges, for example. The host-to-PCI bridge contains queues for posted writes and delayed read requests. All transactions are queued going through the bridge, upstream or downstream. The system bus is superpipelined, in that transactions overlap. A fast burst transactions are allowed between the bridge and main memory, i.e., requests which can be satisfied without deferring or retrying are applied to the system bus without waiting to get a response from the target. A range of addresses (e.g., system memory addresses) is defined to be a fast burst range, and any address in this range is treated differently compared to addresses outside the range. The bridge is programmed, by configuration cycles, to establish this fast burst range, within which it is known that an out-of-order response will not be received. When a transaction reaches a bridge interface from the PCI bus, and it is recognized that the address is within the fast burst range, then the fast burst mode is allowed, and write or read requests can be issued without waiting for the snoop phase, since there is no possibility of defer or retry.

In a method and system of performing a write cycle to a memory address in a multi-processor system, a first write cycle is initiated to the memory address, and a second write cycle is initiated to the memory address. Data from the first and second write cycles is merged, and the merged data is written to the memory address.

Performing a write cycle to memory in a multi-processor system

An apparatus ensures that circuit cards of a computer system are properly oriented and fully inserted into their slots before allowing the computer system to power-up. Each card has two electrically connected key fingers on the card edge, while each slot has first and second contacts adapted to engage the two key fingers when the card is fully seated on the slot. One contact of the first slot is connected to a known voltage, while the second contact is connected to the first contact of the next slot. The second contact of the next slot is in turn connected to the first contact of the subsequent slot. Thus, upon a complete engagement of the cards onto the slots, all contacts are connected in a series arrangement. The final contact is connected to an insertion detector which turns on the computer system power supply only when the voltage of the last contact equals the known voltage, indicating that all circuit cards are fully seated on the slots. Additionally, each circuit card has a card edge with asymmetrical segments which form a mechanical key for ensuring proper orientation of the circuit card on the slot.

Protection of computer system against incorrect card insertion during

An apparatus for handling bus error signals is provided for a computer having a processor, an interrupt controller, a first PCI bus with first PERR# and SERR# signals, and a second PCI bus with second PERR# and SERR# signals. The apparatus has a buffer with an input connected to ground, an enable input connected to the second SERR# signal, and an output connected to the first SERR# signal. When the second SERR# signal is asserted, the first SERR# signal is also asserted via the buffer and is provided to one input of the interrupt controller. In an alternate embodiment, the buffer enable input is connected to the first SERR# signal and the buffer output connected to the second SERR# signal. The apparatus also receives the first and second PERR# signals and logically ORs the signals together to generate a combined PERR# signal. The combined PERR# signal is presented to a register which is clocked by the PCI system clock to synchronize the combined PERR# signal to the PCI clock before presenting the PERR# signal to a second input of the interrupt controller. The interrupt controller generates an interrupt to the processor and causes the processor to poll devices to identify the board that might have caused the error and to take a corrective action.

Bus error handler for PERR# and SERR# on dual PCI bus system

A method for setting host bus clock frequencies and processor core clock ratios in a multi-processor computer system. The method first determines original host bus frequency settings for each of the installed processors. The host bus is set to clock at the slowest of the frequency settings. Processor core clock ratios are then optimized for the new host bus frequency. The optimization process commences by determining the original processor core clock ratio settings for each processor. These ratio settings are individually optimized via an iterative process wherein the core clock ratios are incrementally increased and multiplied by the new host bus frequency. This process continues until the incremented core clock ratio yields a core clock frequency in excess of the maximum rating for the processor under test. The core clock ratio is then decremented and latched into the processor under test via a hard reset. Establishing core clock ratios based on the slowest host bus frequency setting insures that all processors can functionally coexist on a shared host bus and still perform in an optimal manner.

Method and apparatus for establishing host bus clock frequency and

A printed circuit board that includes contact slider regions between conductive pads on the printed circuit board is disclosed. The printed circuit board is particularly suited for high density situations. According to one embodiment, a printed circuit board according to the invention includes a connection edge for insertion into a connector, a first row of conductive pads disposed on one or both sides of the printed circuit board proximate to the connection edge and extending away therefrom in a predetermined direction, and a row of slider regions disposed on one or both sides of the printed circuit board proximate to the connection edge and extending away therefrom in the predetermined direction, the slider regions being interposed between the conductive pads of the first row. The printed circuit board according to the invention is not only more reliable and easier to manufacture, but it also wears substantially better than previously designed high density circuit boards.

Edgecard circuit board

The present invention relates to a fault tolerant system for providing power to a multiple central processing unit computer system. Three DC-DC converters, each sized for providing power to one central processing unit, furnish power to two central processing units through two power planes. Each DC-DC converter has an output voltage level selectable through a voltage identification signal. If the voltage identification signals of the converters match, identification logic couples the power planes together. If only one converter is available to power the two central processing units, a stopclock logic circuit alternatively places the central processing units in known stopclock modes. Thus, the single converter only has to fully power one central processing unit at any one time.

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Longmont, CO, United States of America

Bassam N Elkhoury