Intel Corporation

General Electric Company

Baker Hughes Holdings LLC

Baskaran Ganesan

Tessil Thomas

Suresh Sugumar

Devadatta V Bodas

Russell Jerome Fenger

James Steven Burns

Thanunathan Rangarajan

Sundaravarathan R Iyengar

Gautam Doshi

Feranak Nelson

Mohan J Kumar

Robert Charles Swanson

Mahesh S Natu

Rajesh S Parthasarathy

Frank Binns

Srikanth Balasubramanian

Satish Shrimali

John M Powell, Jr

Rajesh Nagaraja Murthy

Shamanna M Datta

Satheesh Jeyaraman

Albrecht Maurer

Min Huang

Murugasamy K Nachimuthu

Koichi Yamada

Jose Andy Vargas

Suresh K Marisetty

Rahul Pal

Xiaolei Shirley Ao

Binata Bhattacharyya

Manoj Kumar Koyithitta Meethal

Vamshi Krishna Reddy Kommareddy

Shivappa Ningappa Goravar

Edward Randall Furlong

William Johnson Bowhill

Ling Cen

Dheemanth Nagaraj

Alan M Williams

Roger Nordberg

Zhiguo Wang

Eric Dehaemer

Zongqi Sun

Vinod Ambrose

Joseph R Doucette

Sampath Dakshinamurthy

Jim B Crossland

Stan Domen

Binata Bhattacharayya

Vijayanand Naik

Shammanna M Datta

Binoy Balan

Mottito Togo

Harjinder Hullon

Seow Fung Ooi

Yin-Lung Lu

Aibrecht Maurer

Joseph Doucette

Seow Ooi

Shridhar Nath

Matthew Radebach

A method and system for determination of geometric features in an object is provided. The method includes receiving at least one geometric feature response to an ultrasound beam incident on the object. The incident ultrasound beam is produced from one of a plurality of ultrasound transducers. Further, a volumetric representation of the object is generated based on a plurality of object parameters. The volumetric representation of the object and a plurality of transducer parameters are used to generate a predicted beam traversal path in the object. The predicted beam traversal path is utilized to generate a temporal map of predicted time of flight geometric feature response to the ultrasound beam. A position on the volumetric representation of the object is determined as the location of the geometric feature, when the received geometric feature response is equivalent to the predicted time of flight geometric feature response corresponding to the position.

Method and system for determination of geometric features in objects

In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Providing state storage in a processor for system management mode

Providing state storage in a processor for system management mode selectively enabled by register bit instead of external SMRAM

In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Apparatus and method to implement power management of a processor

In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Reducing power consumption of uncore circuitry of a processor

Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. Embodiments of the invention may comprise of logic, modules or any combination thereof, to detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards its respective memory unit(s), a processor core executing a processor low-power mode, and a processor socket (operatively coupling the processing core and the memory unit) executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit(s) and various components of the memory subsystem.

Idle power reduction for memory subsystems

A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

Fault tolerance of multi-processor system with distributed cache

In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Increasing power efficiency of turbo mode operation in a processor

Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.

Efficient frequency boost operation

Embodiments of the invention describe systems and processes directed towards improving link power-management during memory subsystem idle states. Embodiments of the invention control memory link operations when various components of a memory subsystem enter low power states under certain operating conditions. Embodiments of the invention similarly describe exiting low power states for memory links and various components of a memory subsystem upon detecting certain operating conditions. Embodiments of the invention may detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards a memory unit, a processor core executing a processor low-power mode, and a processor socket executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit and various components of the memory subsystem.

Memory link power management

Growing community of inventors

Bengaluru, India

Baskaran Ganesan