Synopsys, Inc.

Basannagouda Somanath Reddy

Deepak Dattatraya Sherlekar

Sai Yaswanth Divvela

Manish Srivastava

Shanie George

Princy K Varghese

Amit Verma

A dynamic flip-flop circuit with a feedback loop includes a input tristate circuit configured to receive a data signal and a clock signal to output a tristate output data signal. The dynamic flip-flop circuit also includes a feedforward circuit configured to receive the tristate output data signal as input to output a feedforward output data signal. The dynamic flip-flop circuit also includes a feedback loop circuit configured to connect the output of the feedforward circuit and the output of the input tristate circuit. The feedback loop circuit includes a transmission gate circuit that is partially on.

Dynamic power efficient low power flip-flop

A circuit includes: a first latch; a second latch coupled to the first latch; and a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch includes: a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter; a first switch connecting the first inverter to a first voltage source; a second switch connecting the first inverter to ground voltage; a third switch connecting the second inverter to the first voltage source; a fourth switch connecting the second inverter to the ground voltage; and a fifth switch connecting the second latch and the first inverter.

Power efficient retention flip flop circuit

On-the-fly multi-bit flip-flop (MBFF) generation is provided by selecting at least two flip-flop blocks from a plurality of candidate flip-flop blocks; identifying a control block from a plurality of candidate control blocks, the control block being identified based on operational specifications of the selected flip-flop blocks; and generating a multi-bit flip-flop instance based on the selected flip-flop blocks and the identified control block.

On-the-fly multi-bit flip flop generation

Two retention flip-flop topologies that utilize a data retention control circuit and a slave/retention latch (sub-circuit) to reliably retain a data bit during standby/sleep operating modes without the need for a local clock signal. The slave/retention latch is controlled using a local clock signal to store sequentially received data bit values during normal operating modes. During standby/sleep modes, the local clock signal is de-activated (i.e., by turning off the supply voltage provided to the local clock generator circuit), and the data retention control circuit operates in accordance with an externally supplied retention enable control signal to both isolate and control the slave/retention latch such that a last-received data bit value is reliably retained in the slave/retention latch. When normal operation is resumed, the local clock signal is re-activated, and the data retention control circuit controls the slave/retention latch to pass the last-received data bit value to an output driver.

Retention flip-flop circuits for low power applications

A circuit is disclosed. The circuit includes an output driver with a pull-up device, and a pull-down device. The circuit also includes a pre-driver, configured to generate a first signal for the pull-up device and to generate a second signal for the pull-down device, a first positive feedback circuit configured to increase the slew rate of the first signal in response to a transition in the second signal, and a second positive feedback circuit configured to increase the slew rate of the second signal in response to a transition in the first signal.

Circuit technique to enhance slew rate for high speed applications

A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.

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Cupertino, CA, United States of America

Basannagouda Somanath Reddy