Texas Instruments Corporation

Basab Chatterjee

Richard L Guldi

Jeffrey Alan West

Thomas Dyer Bonifield

Satyavolu Papa Rao

Mona M Eissa

Vincent C Korthuis

Satyavolu Srinivas Papa Rao

Gregory Boyd Shinn

Phillip D Matz

Sopa Chevacharoenkul

Kenneth Joseph Newton

Keith W Melcher

Ju-Ai Ruan

Chris D Atkinson

Barry Lanier

Anand J Reddy

Shangting Detweiler

Ching-Te Lin

Chad J Kaneshige

An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

Crack deflector structure for improving semiconductor device robustness against saw-induced damage

An integrated circuit substrate containing an electrical probe pad structure over, and on both sides of, a dicing kerf lane. The electrical probe pad structure includes metal crack arresting strips adjacent to the dicing kerf lane. A metal density between the crack arresting strips is less than 70 percent. An electrical probe pad structure containing metal crack arresting strips, with a metal density between the crack arresting strips less than 70 percent. A process of forming an integrated circuit by forming an electrical probe pad structure over a dicing kerf lane adjacent to the integrated circuit, such that the electrical probe pad structure has metal crack arresting strips adjacent to the dicing kerf lane, and performing a dicing operation through the electrical probe pad structure.

Replacement of scribeline padframe with saw-friendly design

In accordance with the invention, there are semiconductor devices and methods of making semiconductor devices and holes. The method of making a semiconductor device can comprise forming a photoresist layer over a surface of a wafer, wherein the wafer comprises an edge that has a substantially rounded profile, an array of dies, and at least one edge die. The method can also comprise dividing a shot area into a plurality of shot portions and assigning a blind ID to each of the plurality of shot portions. The method can further comprise identifying one or more edge shot portions on the edge of the wafer for additional exposure; and exposing one or more times identified one or more edge shot portions on the edge of the wafer and blocking non-identified one or more non-edge shot portions.

By-die-exposure for patterning of holes in edge die

A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Reduction of punch-thru defects in damascene processing

The present invention provides, in one embodiment, a method () of manufacturing a semiconductor device. A conventionally formed reticle is positioned over a resist located on a substrate (). A radiation path through the reticle and a window assembly located between a radiation source and resist (), is considered. It is determined whether or not the radiation would expose a predefined blocking area of the resist within the exposure zone (). If the radiation would expose a blocking area, then the window assembly is configured to prevent radiation from exposing the blocking area in the exposure zone (). Other embodiments include a window assembly () and system () to facilitate manufacturing of the semiconductor device according to the method ().

Adjustable lithography blocking device and method

An x-ray confocal defect detection system comprises an x-ray source, a confocal component, and defect detectors and operates on a target portion of a semiconductor device. The x-ray source generates x-ray energy. The semiconductor device includes a plurality of formed layers. The target portion is a selected layer or portion of the plurality of formed layers. At least a portion of the x-ray is transmitted through the semiconductor device as transmitted x-ray. The confocal component receives the transmitted x-ray and passes target x-ray intensity from the target portion of the transmitted x-ray energy. Detectors receive the target x-ray from the confocal component from which defect analysis can be performed.

X-ray confocal defect detection systems and methods

A system ( ) for detecting defects in a semiconductor wafer ( ), such defects including voids (V) present in metal conductors ( ) and plugs ( ), is disclosed. An x-ray source ( ) irradiates the wafer ( ) through a first aperture array ( ) having openings ( ); a second aperture array ( ) is located on the opposite side of the wafer ( ) from the source ( ), and has openings ( ) that are aligned and registered with the openings ( ) in the first aperture array ( ). An array of x-ray detectors ( ) is located adjacent to the second aperture array ( ), with each detector ( ) associated with one of the openings ( ) of the second aperture array ( ). The detectors ( ) communicate signals regarding the magnitude of x-ray energy that is transmitted through wafer ( ) at locations defined by the openings ( ) through aperture arrays ( ), to an analysis computer ( ). A wafer translation system ( ) indexes or otherwise moves the wafer ( ) between the aperture arrays ( ). The analysis computer ( ) generates an x-ray image of the wafer ( ) from the detected x-ray energy, or alternatively compares the detected x-ray energy at locations of wafer ( ) to automatically detect and distinguish defects.

X-ray defect detection in integrated circuit metallization

A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer. The process also includes the steps of simultaneously buffing a second wafer with the buffing pad for a second length of time, in which the first length of time is greater than the second length of time, and rinsing the buffing pad and the buffed wafer with a moisture maintenance compound for at least a portion of the time between the completion of the second length of time and the first length of time. Moreover, the moisture maintenance compound substantially prevents drying of the buffed wafer between the completion of the second length of time and the first length of time.

Growing community of inventors

Allen, TX, United States of America

Basab Chatterjee