Netlogic Microsystems, Inc

Cypress Semiconductor Corporation

Bartosz Banachowicz

Andrew J Wright

Dinesh Maheshwari

Bin Jiang

Roger J Bettman

Fuad Badrieh

Feng Dai

A ternary content addressable memory (TCAM) cell circuit formed in a TCAM memory cell array having cells arranged in rows and columns can include a first storage circuit with first and second data path, a second storage circuit with a third and fourth data path, and a compare circuit. No more than four conductive lines in a column wise direction have a direct electrical connection to the TCAM cell. Such conductive lines can include a first bit line coupled to the first data path and the third data path and a second bit line coupled to the second data path and the fourth data path.

Ternary content addressable memory (TCAM) cells with low signal line numbers

A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell () can include a pair of memory areas to store data (----), and a logic portion (--) that receives the data stored therein. Memory areas and the logic portions of each memory/logic cell can be arranged on the substrate in a shape of an L, U, S, T, or Z to form a pair of interlocking memory/logic cells.

Interlocking memory/logic cell layout and method of manufacture

In one embodiment, an electrically conductive trench in an integrated circuit allows for the formation of capacitors between the trench and other portions of the integrated circuit. For example, a capacitor may be formed between the trench and an electrically conductive line. Among other advantages, the capacitor provides a relatively large capacitance while occupying a relatively small area.

Trench-based capacitor for integrated circuits

Growing community of inventors

Santa Clara, CA, United States of America

Bartosz Banachowicz