Globalfoundries Inc.

Globalfoundries U.S. Inc.

Nxp B.v.

Imec Vzw

Imec

Koninklijke Philips Corporation N.V.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Interuniversitair Microelektronica Centrum (imec)

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Bartlomiej Jan Pawlak

Ajey Poovannummoottil Jacob

Yusheng Bian

Steven J Bentley

Michal Rakowski

Luke G England

Puneet Harischandra Suvarna

Geert Eneman

Behtash Behin-Aein

Raymond James Duffy

Mehdi Salmani-Jelodar

Ruilong Xie

Julien Frougier

Steven M Shank

Lars W Liebmann

Judson Robert Holt

Siva P Adusumilli

Daniel Chanemougame

Guillaume Bouche

Bipul C Paul

Murat Kerem Akarvardar

Nicholas V Licausi

Deepak K Nayak

Andreas Knorr

Srinivasa Banna

Nicholas A Polomoff

Philippe Meunier-Beillard

Ramsey M Hazbun

Liesbeth Witters

Geoffrey Pourtois

Koushik Ramachandran

Oscar Restrepo

Dmitry Yakimets

Christian A Witt

Eduardo Cruz Silva

Tom Janssens

Richard Lindsay

Bartlomiej Sojka

Pieter Schuddinck

Clement J E Porret

Srinivasan Ashwyn Srinivasan

Disclosed is a semiconductor structure including a monocrystalline silicon layer having a first surface and a second surface opposite the first surface. A cavity extends into the first semiconductor layer at the second surface. The structure also includes a polycrystalline silicon layer adjacent to the second surface and extending over the cavity. At least one opening extends through the second semiconductor layer to the cavity.

Microfluidic channel structure and method

Structures including an edge coupler and methods of forming such structures. The structure comprises a dielectric layer on a semiconductor substrate. The dielectric layer includes a cavity and an edge defining a boundary of the cavity. The structure further comprises an edge coupler including a waveguide core. The waveguide core includes a portion that extends past the edge of the dielectric layer and overhangs the cavity. The structure further comprises a heater positioned adjacent to the portion of the waveguide core. The heater is spaced by a gap from the portion of the waveguide core.

Edge couplers with a fine-alignment mechanism

Structures including an electro-absorption modulator and methods of forming such structures. The structure comprises a waveguide core including a first tapered section, a second tapered section, and a longitudinal axis. The first tapered section and the second tapered section are aligned along the longitudinal axis. The structure further comprises a first waveguide taper overlapping the first tapered section of the waveguide core, a second waveguide taper overlapping the second tapered section of the waveguide core, and a multiple-layer structure on the waveguide core between the first waveguide taper and the second waveguide taper.

Electro-absorption modulators with stacked waveguide tapers

Structures including stacked photonics chips and methods of fabricating a structure including stacked photonics chips. The structure comprises a first chip including a first waveguide core, a ring resonator adjacent to a portion of the first waveguide core, and a first dielectric layer over the first waveguide core and the ring resonator. The first dielectric layer has a first surface. The structure further comprises a second chip including a second waveguide core and a second dielectric layer over the second waveguide core. The second dielectric layer has a second surface adjacent to the first surface of the first dielectric layer, and the second waveguide core is positioned adjacent to the ring resonator.

Light coupling between stacked photonics chips

The disclosed subject matter relates generally to photonic integrated circuit chips, semiconductor assemblies or packagings, and a method of forming the same. More particularly, the present disclosure relates to placement of optical fibers on a photonics chip, and a semiconductor assembly including the photonics chip.

Photonics chips and semiconductor products having angled optical fibers

Disclosed is a structure (e.g., a lab-on-chip structure) including a substrate, an insulator layer on the substrate, and at least one optical ring resonator. Each ring resonator includes cladding material on the insulator layer and, embedded within the cladding material, a first waveguide core with an input and an output, and second waveguide core(s) (e.g., ring waveguide core(s)) positioned laterally adjacent to the first waveguide core. A reservoir is below the ring resonator within the insulator layer and substrate such that surfaces of the waveguide cores are exposed within the reservoir. During a sensing operation, the waveguide core surfaces contact with fluid within the reservoir and a light signal at the output of the first waveguide core is monitored (e.g., by a sensing circuit, which in some embodiments is also coupled to a reference optical ring resonator) and used, for example, for spectrum-based target identification and, optionally, characterization.

Optical ring resonator-based microfluidic sensor

Structures for an optical power modulator and methods of fabricating a structure for an optical power modulator. A waveguide core includes a longitudinal axis, a first section, and a second section spaced from the first section along the longitudinal axis. An active layer includes a portion positioned along the longitudinal axis between the first section and the second section of the waveguide core. The active layer contains a material configured to have a first state with a first refractive index in response to an applied stimulus and a second state with a second refractive index different from the first refractive index.

Optical power modulators based on total internal reflection

According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

Semiconductor fin structure and method of fabricating the same

Disclosed is a memory cell including parallel-connected first access transistors and a first variable resistor in series between a bitline and a source line and parallel-connected second access transistors and a second variable resistor in series between the bitline and the source line. A write wordline controls one pair of first and second access transistors so that, during an initialization mode, the resistors are concurrently subjected to the same write bias conditions for one-time programming to switch from an unprogrammed state (where the resistors have the same first resistance state) to a programmed state (where one resistor has switched to a second resistance state and a bit is stored). Discrete first and second read wordlines control another pair of first and second access transistors to enable discrete read processes associated with the first and second variable resistors. Also disclosed are an associated circuit (e.g., a PUF) and a method.

Physically unclonable function architecture including memory cells with parallel-connected access transistors and common write wordlines

Disclosed is a quantum-confined Stark effect (QCSE) modulator. In the modulator, a first doped semiconductor region has a first type conductivity, is at the bottom of a trench in a dielectric layer and is immediately adjacent to a semiconductor layer. An MQW region is in the trench on the first doped semiconductor region and at least upper segments of sidewalls of the MQW region are angled away from adjacent sidewalls of the trench such that there are spaces between the MQW region and the dielectric layer. Dielectric spacers fill the spaces. A second doped semiconductor region has a second type conductivity, is on top of the MQW region and optionally extends laterally onto the tops of the dielectric spacers. The spacers prevent shorting of the doped semiconductor regions. Also disclosed are embodiments of a photonics structure including the modulator and of methods for forming the modulator and the photonics structure.

Quantum-confined stark effect (QCSE) modulator and photonics structure incorporating the QCSE modulator

The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.

Micro-LED display assembly

A method includes forming a first circuit element in and above a first semiconductor layer, the first semiconductor layer being formed on a first buried insulating layer, forming drain and source regions of the first circuit element at least partially in the first semiconductor layer, and forming a layer stack above the first circuit element, the layer stack including a conductive layer, a second buried insulating layer formed above the conductive layer, and a second semiconductor layer formed above the second buried insulating layer, wherein the conductive layer is electrically isolated from the drain and source regions.

Methods of forming stacked SOI semiconductor devices with back bias mechanism

Disclosed are structures (e.g., a fin-type field effect transistor (FINFET) and a nanowire-type FET (NWFET)) and methods of forming the structures. In the methods, a fin is formed. For a FINFET, the fin includes a first semiconductor material. For an NWFET, the fin includes alternating layers of first and second semiconductor materials. A gate is formed on the fin. Recesses are formed in the fin adjacent to the gate and extend to (or into) a semiconductor layer, below, made of the second semiconductor material. An oxidation process forms oxide layers on exposed semiconductor surfaces in the recesses including a first oxide material on the first semiconductor material and a second oxide material on the second semiconductor material. The first oxide material is then selectively removed and source/drain regions are formed by lateral epitaxial deposition in the recesses. The remaining second oxide material minimizes sub-channel region source-to-drain leakage.

Methods of forming a bulk field effect transistor (FET) with sub-source/drain isolation layers and the resulting structures

Disclosed herein are a method of forming stacked elongated nanoshapes (NSs) (e.g., stacked nanowires (NWs)) of different semiconductor materials above a substrate, a method of forming different devices (e.g., stacked field effect transistors (FETs) having different type conductivities) using the stacked NSs and the resulting structures. In the methods, stacked elongated NSs made of the same first semiconductor material can be formed above a substrate. The stacked elongated NSs can include at least a first NS and a second NS above the first NS. The second NS can then be selectively processed in order to convert the second NS from the first semiconductor material to a second semiconductor material. The first and second NSs can subsequently be used to form first and second devices, respectively, wherein the second device is stacked above the first device. The first and second device can be, for example, first and second FETs, respectively.

Stacked elongated nanoshapes of different semiconductor materials and structures that incorporate the nanoshapes

A semiconductor device includes at least two stacked SOI levels or configurations, each of which may include transistor elements formed on the basis of a given technology node. At least the uppermost device level may include a back bias mechanism for providing superior controllability of the respective transistor elements. In some illustrative embodiments, at least two of the stacked SOI configurations may have implemented therein a back bias mechanism, wherein an appropriate contact regime is provided so as to connect to the respective conductive regions or layers below the corresponding buried insulating layers for each stacked device level. Consequently, increased lateral packing density may be accomplished on the basis of a given technology node.

Stacked SOI semiconductor devices with back bias mechanism

Growing community of inventors

Leuven, Belgium

Bartlomiej Jan Pawlak