Imec Vzw

Imec

Katholieke Universiteit Leuven

Katholieke Universiteit Leuven, Ku Leuven R&d

Universiteit Antwerpen

Bart Soree

Wim Magnus

Marc Marcel Heyns

Geoffrey Pourtois

Hanns Christoph Adelmann

Odysseas Zografos

Florin Ciubotaru

Amirhasan Nourbakhsh

Mohammad Ali Pourghaderi

Ahmed Kenawy

Dimitrios Andrikopoulos

Maarten Thewissen

Tarun Kumar Agarwal

The disclosed technology generally relates to superconducting devices, and more particularly to superconducting rings, qubits comprising the superconducting rings and methods of coherently coupling flux states of the superconducting rings. In one aspect, a qubit includes a superconducting ring around a hole. The qubit additionally includes an electric field generator adapted for applying an electric field in a plane of the superconducting ring over at least part of the superconducting ring, and a magnetic field generator adapted for applying a magnetic field component orthogonal to the plane of the superconducting ring such that the magnetic field component at least crosses the hole of the ring.

Quantum bits by electrostatic gating superconducting rings

The disclosed technology generally relates to computation devices, and more particularly to majority gate devices configured for computation based on spin waves. In one aspect, a majority gate device comprises cells that are configurable as spin wave generators or spin wave detectors. The majority gate device comprises an odd number of spin wave generators, and at least one spin wave detector. The majority gate device additionally comprises a waveguide adapted for guiding spin waves generated by the spin wave generators. The spin wave generators and the at least one spin wave detector are positioned in an inline configuration along the waveguide such that, in operation, interference of the spin waves generated by the spin wave generators can be detected by the at least one spin wave detector. The interference of the spin waves corresponds to a majority operation of the spin waves generated by the spin wave generators.

Wave-based majority gate device

A solid-state device configured to generate an electric signal indicative of a presence or an absence of a magnetic topological soliton is disclosed. The solid-state device includes a storage element configured to store a magnetic topological soliton. The storage element includes a topological insulator. The storage element also includes a magnetic strip arranged on the topological insulator. The solid-state device also includes a magnetic topological soliton detector configured to generate the electric signal indicative of the presence or the absence of the magnetic topological soliton in a detection region of the storage element. The magnetic topological soliton detector is adapted for detecting a spin-independent difference in tunneling amplitude, a difference in electrical resistance, or a difference in electrical conductivity through the topological insulator in the detection region due to the presence or the absence of the magnetic topological soliton in the detection region.

Magnetic topological soliton detection

The present disclosure relates to semiconductor devices with gate-controlled energy filtering. One example embodiment includes a semiconductor device. The semiconductor device includes a first electrode, a second electrode, and a channel therebetween. The semiconductor device also includes a first interference structure located in the channel. Further, the semiconductor device includes a first gate for controlling a voltage over the first interference structure. The first interference structure is formed to induce a local mini-band structure that can be shifted by the voltage controlled by the first gate, such that the first local mini-band structure is: (1) aligned with a band structure in the semiconductor device to turn the semiconductor device on; and (2) misaligned with the band structure in the semiconductor device to turn the semiconductor device off.

Semiconductor devices with gate-controlled energy filtering

A bilayer graphene tunnelling field effect transistor is provided comprising a bilayer graphene layer, and at least a top gate electrode and a bottom gate electrode, wherein the at least a top gate electrode and a bottom electrode are appropriately positioned relative to one another so that the following regions are electrically induced in the chemically undoped bilayer graphene layer upon appropriate biasing of the gate electrodes: a source region, a channel region, and a drain region.

Bilayer graphene tunneling field effect transistor

A spin transfer torque magnetic memory device is disclosed. In one aspect, the spin transfer torque magnetic memory device comprises a first layered structure stacked in a vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device additionally includes a second layered structure stacked in the vertical direction and comprising alternating topological insulator layers and insulator layers. The memory device further includes a magnetic material interposing the first and second layered structures in a horizontal direction different from the vertical direction such that the magnetic material is in contact with a first side surface of the first layered structure and in contact with a first side surface of the second layered structure. Additionally, the magnetic material is configured to have a magnetization direction that can change in response to a current flowing through the magnetic material.

Spin transfer torque magnetic memory device

A heterostructure field effect transistor is provided comprising a semiconductor wire comprising in its longitudinal direction a source and a drain region, a channel region in between the source and drain region and in its transversal direction for the source region, a source core region and a source shell region disposed around the source core region, the source shell region having in its transversal direction for the drain region, a drain core region and a drain shell region disposed around the drain core region, the drain shell region having in its transversal direction for the channel region, a channel core region and a channel shell region disposed around the channel core region; wherein the thickness of the channel shell region is smaller than the thickness of the source shell region and is smaller than the thickness of the drain shell region.

Semiconductor heterostructure field effect transistor and method for making thereof

A novel nanostructure device operating in Junction Field Effect Transistor (JFET) mode is provided that avoids the majority of the carriers that interact with the interface (e.g. surface roughness, high-k scattering).

Growing community of inventors

Begijnendijk, Belgium

Bart Soree