Xilinx, Inc.

Triscend Corporation

Bart Reynolds

Keith R Bean

Daniel P Kirkwood

James F Barei

Benjamin D Ralston

Sridhar Krishnamurthy

Matthew H Klein

Brian Fox

Xiaojian Yang

Steven Winegarden

Kai Zhu

Damon McCormick

Stephen M Trimberger

Jean-Didier Allegrucci

Fung Fung Lee

Ian L McEwen

Wilson Kaming Yee

Pradip Jha

Andreas Papaliolios

Arye Ziklik

Danesh Tavana

Cheng-I Chuang

Dinesh K Monga

Tom Shui

Chong M Lee

Brendan Matthew O'Higgins

Chukwuweta Chukwudebe

Ryan Linderman

Christine M Weir

Todd J Topolewski

Jennifer D McEwen

Stanley S Yang

Pardner Wynn

Julia M Smuts

A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.

Unified data model for heterogeneous integrated circuit

Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.

Programmable integrated circuits for emulation

Rendering a graphical representation of an integrated circuit can include determining, using a processor, a tile of a device model at least partially within a viewport, determining, using the processor, an owning tile having a fly-over wire passing over the tile, determining, using the processor, a predetermined shape of the fly-over wire, and drawing, using the processor, the fly-over wire within the viewport based upon the shape.

Device graphics rendering for electronic designs

A processor-implemented method is provided for constructing a model of a programmable logic device (PLD) design. A netlist is input that describes the PLD design. An identification is input of programmable tile modules that include a programmable resource, which is either programmable interconnect or programmable logic. A first characterization data is input for sub-modules of the programmable tile modules for the programmable resource. For each programmable tile module, the routing arcs of each programmable interconnect are generated. A second characterization data is input for a configuration memory cell module of the PLD design. A third characterization data is input for a configuration control module of the PLD design. A first map is generated that links each routing arc to a bit of configuration data for programming the programmable interconnect. A second map is generated that links each logic function to a bit of configuration data for programming the programmable logic.

Constructing a model of a programmable logic device

A processor-implemented method is provided for determining networks of a tile module of a programmable logic device (PLD) design. A netlist describing the PLD design and a tile module identification are input. Characterization data is input for a sub-module of the tile module that specifies modeled pins of the sub-module, which is either a switchbox or a logic site. Connectivity pins of the tile module are determined. Each connectivity pin of one of the tile instances is connected in the netlist to a modeled pin of an instance of the sub-module within a tile instance. Networks of the tile module are determined that connect a first subset of the connectivity pins of the tile module and a second subset of the modeled pins of an instance of the sub-module within the tile module. A specification is output for each of the networks including the first subset and the second subset.

Determining networks of a tile module of a programmable logic device

A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design. The netlist and an identification of each tile are input. For each of the tiles, a specification is input of a graphical tile representation and connection representations that terminate at a boundary of the tile representation. A specification is input of an arrayed placement of occurrences of the tile representations. For each abutting pair of occurrences of the tile representations in the arrayed placement, the connection representations are determined that terminate at a shared portion of the boundaries of the tile representations of the abutting pair. For each of a plurality of positions within the shared portion of the boundaries of the tile representations of each abutting pair, a match is checked between the connection representations terminating at the position.

Comparing graphical and netlist connections of a programmable logic device

A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile module are input. Characterization data is input for a sub-module of the tile module that specifies a select input pin controlling a programmable function of the sub-module, which is either a multiplexer or a logic site. Characterization data is input for a configuration memory cell of the tile module that specifies a data output pin of the configuration memory cell. The controlling pin is determined for each select input pin of each instance of the sub-module of the tile module. The controlling pin of a select input pin is the data output pin of an instance of a configuration memory cell of the tile module. A specification is output of the select input pin and corresponding controlling pin.

Determining controlling pins for a tile module of a programmable logic device

A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell instances of the configuration memory cell. An identification of the tile module is input. Characterization data is input for each configuration memory cell specifying address and data input pins. Characterization data is input for each configuration control module specifying a first ordered set of address output pins and a second ordered set of data output pins. For each of the cell instances, the first index of an address output pin in the first ordered set and the second index of a data output pin in the second ordered set are determined and a specification is output of the cell instance and the first and second indices.

Determining indices of configuration memory cell modules of a programmable logic device

A processor-implemented method is provided for determining programmable connections through a switchbox module of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of the switchbox module are input. Characterization data is input for each multiplexer module of the switchbox module. The characterization data specifies input pins and at least one output pin of the multiplexer module. The multiplexer module programmably connects each output pin to one of the input pins. Pins of the switchbox module are determined through which the programmable connections are provided via an instance of a multiplexer module of the switchbox module. Each pair of the pins of the switchbox module is determined that are functionally connected via at least one instance of the at least one multiplexer module, with each pair specifying a programmable connection. A specification of the programmable connections is output.

Determining programmable connections through a switchbox of a programmable logic device

A processor-implemented method is provided for determining reachable pins functionally connected to a network of a netlist that describes a programmable logic device (PLD) design. A netlist and an identification of the network in the netlist are input. Characterization data is input for one or more repeater modules that specify a first set of functionally connected pins of the repeater module. A second set is initialized with the pins of the network. For each pin in the second set that is one of the functionally connected pins of a first set, an additional pin may be added to the second set for each of the pins of a network for each of the functionally connected pins. The adding is repeated for each additional pin added to the second set. A specification of the pins from the second set is output as the reachable pins.

Determining reachable pins of a network of a programmable logic device

In one embodiment, a method for specifying addressability in a memory-mapped device is disclosed. A data access primitive is used to model addressablity for the memory-mapped device. Addressability comprises an address matching function, a lane matching function and one or more bus connections. A first starting address for the memory-mapped device is specified. A first set of addressing matching function, lane matching function and one or more bus connections for the memory-mapped device is generated using the data access primitive and the first starting address.

Method and apparatus for specifying addressability and bus connections in a logic design

Interface logic is disclosed. The interface logic comprises a first address decoder, a first set of mode logic coupled to the address decoder and a first selector coupled to the first set of mode logic. The interface logic is adaptable to connect the programmable logic to the system interconnect via one of a plurality of access modes supported by the system interconnect.

Programmable interface for a configurable system bus

A method and apparatus for determining a width of an external memory is described. The method comprises reading a data from memory, and if the data matches an expected data key, determining the width of the memory.

Method and apparatus for determining the width of a memory subsystem

A bidirectional bus structure includes a first multiplexer path propagating signals in a first direction and a second multiplexer path propagating signals in a second direction. For one embodiment, the bus structure further includes a circuit for selectively combining the signals on the first and second paths and selectively propagating the signal on one of the first and second paths. For another embodiment, the bus structure further includes a logic gate for combining the signals on the first and second paths and a circuit for selectively propagating the signal on one of the first path, the second path, and an output signal of the logic gate. For both embodiments, the present invention allows multiple signals to use the bus without contention, thereby providing an extremely flexible interconnect routing resource. This bidirectional bus can selectively drive signals onto the general interconnect as well as onto a system bus in a configurable system on a chip.

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Seattle, WA, United States of America

Bart Reynolds