Intel Corporation

Motorola Corporation

Bart R McDaniel

Lawrence T Clark

Kevin William Glass

Waleed Khalil

Jay S Heeb

Tom J Adelmeyer

Keng L Wong

Edward John Bawolek

Malcolm Harold Smith

Mark A Beiley

Eric J Hoffman

David R Allee

Yueming He

James T Doyle

Alexander Waizman

According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a pulse generator to provide a low voltage source, a transformer coupled to the pulse generator to boost a voltage received from the pulse generator and a switch component coupled to the pulse generator. The switch component includes an actuation capacitor to store charge associated with the voltage received from the transformer.

Low voltage microelectromechanical RF switch architecture

An N-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.

Sigma-delta conversion with analog, nonvolatile trimmed quantized feedback

Briefly, in accordance with an embodiment of the invention, a method and circuit to perform an analog-to-digital conversion is provided. The method may include generating and storing a combined charge which is generated by combining an input charge and a reference charge.

Method and apparatus to perform an analog to digital conversion

Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Method and apparatus for dynamic power control of a low power processor

A buffer circuit includes an amplifier, a pass gate circuit and a level shifter. The pass gate circuit communicates an input signal to the amplifiers and includes a terminal to control the communication. A level shifter furnishes a control signal to the terminal of the pass gate circuit and regulates the control signal based on a magnitude of the input signal.

Buffer circuit

An analog-to-digital converter (ADC) is provided. The analog-to-digital converter includes a plurality of differential comparators. For each of the plurality of differential comparators the ADC receives differential input signals and differential reference signals and generates an output signal. The ADC also includes a self-calibration circuit to receive from each of the plurality of differential comparators the output signal. In response to the output signal, the self-calibration circuit generates a self-calibration signal. The ADC further includes an adjustable reference signal generator to provide the differential reference signals based on the self-calibration signal.

CMOS flash analog to digital converter compensation

In one embodiment, the present invention provides a circuit that includes a core circuit and a control circuit coupled to the core circuit. The control circuit reduces a leakage current in the core circuit when the core circuit is in a Sleep mode. The control circuit maintains a logic state of the core circuit when the core circuit is in a Drowsy mode.

Integrated circuit low leakage power circuitry for use with an advanced

A method and apparatus for performing analog to digital conversion. A voltage to current converter converts an analog input voltage to an input current. A current reference generates a reference current. A plurality of scaling elements scaled the reference current to yield a plurality of scaled reference currents each corresponding to some voltage level within the dynamic range of the input voltage. The input current is compared to each of the scaled reference currents in a plurality of current comparators to generate a thermometer code from which a digital representation of the analog input voltage is derived.

Electronic system with high speed, low power, A/D converter

An image sensor having a well-to-substrate diode as the photodetector. In a preferred embodiment, a modern salicided (CMOS) process is utilized to manufacture the image sensor. The field oxide region above the diode junction is transparent to visible light, thus allowing the photodiode competitive quantum efficiency as compared to devices having source/drain diffusion-to-substrate photodiodes fabricated on a non-salicided process. The photodiode can be integrated as part of a sensor array with digital circuitry using a relatively unmodified digital CMOS process. Furthermore, the structure allows the optical properties of the photodiode to be engineered by modifying the well without deleterious effects, to approximate a first order, on the characteristics of a FET built in another identical well.

Well to substrate photodiode for use in a CMOS sensor on a salicide

Ultra high speed, low power, flash A/D converter utilizing a current

A method and apparatus for selectively enabling individual sets of registers in a row of a register array. One embodiment of the present invention is a register array that has a number of registers arranged in a number of rows and columns. Each row of registers includes N sets of registers, where N is an integer greater than 1. The register array also includes a said selector and N said-selecting enable lines for each row of registers. Each enable line of the N set-selecting enable lines couple the set selector to one set of registers of the N sets of registers in each row. In other words, the set selector enables a particular set of registers (i.e., causes a particular set of registers to output their contents on their output bit lines) by providing an enable signal to the particular set of registers on the enable line that couples the set selector to the particular set of registers.

Method and apparatus for selectively enabling individual sets of

A current regenerative comparator. A pair of cross coupled inverters are coupled to an equalizing transistor, an input current mirror and a reference current mirror, such that current flowing in the input current mirror is compared to the current flowing in the reference current mirror.

High speed, low power, current mode comparator

A common centroid differential sensing apparatus for sensing the contents of registers in a register array. This differential sensing apparatus includes a first pair of differential bit lines, which traverse across the register array in a predetermined direction (e.g., traverse the length or the width of the array) along a first traversing path or a second traversing path. This differential sensing apparatus also includes a second pair of differential bit lines, which traverse across the register array in the predetermined direction along a third traversing path and a fourth traversing path. Furthermore, the bit lines of one of the pairs of differential bit lines swap every ##EQU1## from the top and the bottom of the register array and swap every ##EQU2## afterwards, while the bit line pairs of the other of the pairs of the differential bit lines swap at ##EQU3## from the top and the bottom of the register array and every ##EQU4## afterwards, where N is an integer greater than 0.

Common centroid differential sensing scheme

A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.

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Phoenix, AZ, United States of America

Bart R McDaniel