Koninklijke Philips Corporation N.v.

Bart Mesman

Jan Hoogerbrugge

Jeroen Anton Johan Leijten

Marco Jan Gerrit Bekooij

Adrianus Josephus Bink

Johan Sebastiaan Henri Van Gageldonk

Cornelis Arnoldus Josephus Van Eijk

The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means. Further, the present invention relates to a method for processing digital signals in a digital signal processing apparatus comprising a plurality of available hardware resource means, wherein at least a part of said hardware resource means execute operations under control of a first instruction set, and wherein at least a part of a predetermined limited subset of said plurality of available hardware resource means execute operations under control of a second instruction set having access to only said predetermined limited subset of said hardware resource means.

Interruptible digital signal processor having two instruction sets

A signal processing device and method of supplying a signal processing result to a plurality of registers arranged in different register files. A plurality of different register files are selected based on a corresponding indication in said instruction word and the register address is supplied to said selected register files. Result values can be broadcasted to multiple registers in a single processor cycle while a copy operation between different register files is eliminated. Broadcasting is thus implemented via overlapping register address spaces, since physical registers having the same logical register address are provided in different register files.

Signal processing device and method for supplying a signal processing result to a plurality of registers

The present invention relates to a compiling method and system for generating a sequence of program instructions for use in a processing architecture with architecture resources executing instructions from a corresponding instruction set. A retargetable compiler is used to generate a code using at least two instruction sets in the same processing architecture. One instruction set for a compact code and one for a parallel high performance code. The compact instruction set (Compact Instruction Format) covers a subset (RF, ALU, L/S, BU) of the architecture, whereas the complete instruction set covers the entire architecture (RF, UC, UCRFUCUCRFUCUCRFUC). By using the at least two instruction sets of different sizes, the compiler is able to reduce the processed average code length, since fewer bits are needed in the compact code to encode operations and registers.

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Eindhoven, Netherlands

Bart Mesman