Sarnoff Corporation

Sofics Bvba

Sarnoff Europe

Sarnoff Europe Bvba

Bart Keppens

John Armer

Markus Paul Josef Mergens

Benjamin Van Camp

Koen Gerard Maria Verhaege

Phillip Czeslaw Jozwiak

Cornelius Christian Russ

Geert Wybo

Koen Verhaege

Frederic Marie Dominique De Ranter

Frederic De Ranter

Cong Son Trinh

An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.

Device having a low-voltage trigger element

A method and apparatus for providing ESD event protection for a circuit using a source or bulk pump to increase the bulk and/or source potential level during an ESD event. The apparatus comprises a protection circuit that, in response to an ESD event, limits the voltage formed between two terminals of a transistor by adjusting a potential level on the second terminal.

Method and apparatus for protecting a gate oxide using source/bulk pumping

A method and apparatus for providing ESD protection. An ESD clamp is connected across the terminals to be protected circuit. The clamp is coupled to a current detector that activates the clamp when current from an ESD event exceeds a predefined limit.

Method and apparatus for providing current controlled electrostatic discharge protection

An electrostatic discharge (ESD) MOS transistor including a plurality of interleaved fingers, where the MOS transistor is formed in an I/O periphery of and integrated circuit (IC) for providing ESD protection for the IC. The MOS transistor includes a P-substrate and a Pwell disposed over the P-substrate. The plurality of interleaved fingers each include an N+ source region, an N+ drain region, and a gate region formed over a channel region disposed between the source and drain regions. Each source and drain includes a row of contacts that is shared by an adjacent finger, wherein each contact hole in each contact row has a distance to the gate region defined under minimum design rules for core functional elements of the IC. The Pwell forms a common parasitic bipolar junction transistor base for contemporaneously triggering each finger of the MOS transistor during an ESD event.

Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling

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Gistel, Belgium

Bart Keppens