Alcatel N.v.

Nokia Solutions and Networks Oy

Alcatel Lucent

Alcatel

Bart J Pauwels

Michel A Henrion

Henri A Verhille

Carl Mertens

Koenraad Schelfhout

Michel P De Somer

Jochen Maes

Yannick Lefevre

Denis J Mestdagh

Werner Van Hoof

Eric Van Den Berg

Yves Therasse

Michael Fivez

Michaël Fivez

Filip Callens

Robertus J Van Engelshoven

Raymond D Wulleman

Jozef A Goubert

Example embodiments describe an optical line terminal, OLT, configured to perform determining a fragmentation allocation for respective ONUs; and notifying, the respective ONUs, of the fragmentation allocation. Other example embodiments relate to an optical network unit, ONU, configured to perform receiving, from the OLT, fragmentation allocation for fragmenting one or more packets; processing the packets in accordance with the fragmentation allocation to obtain fragmented and unfragmented packets; and forwarding, to the OLT, the fragmented and unfragmented packets in accordance with the dynamic upstream allocation map.

Optical line terminal and an optical network unit

A distribution network with point-to-multipoint architecture couples a line termination unit to a plurality of network termination units. A network termination unit includes one or more user network interfaces configured to interface with respective user equipment of respective users, a downstream packet buffer for temporary storage of data packets, a downstream packet buffer monitor configured to monitor the status of the downstream packet buffer and to generate back-pressure signals indicative for the status, wherein the status corresponds to a fill level or fill level variation of the downstream packet buffer, and an upstream transmitter configured to upstream transmit the back-pressure signals to the line termination unit to be used there for shaping and/or scheduling future downstream transmission of data packets to the one or more user network interfaces.

Network termination unit and line termination unit

Example embodiments describe a transmitter including data encapsulation circuitry configured to encapsulate data packets into Data Transport Units, DTUs, for further transmission over a communication medium. The data packets have respective Quality of Service, QoS, tolerances. The data encapsulation circuitry is configured to delay transmission of first data packets with a lower QoS tolerance and to group the first data packets in a subset of DTUs available for transportation of the first data packets.

Encapsulation of data packets

System for producing a system clock signal comprising a local oscillator configured to generate a first clock signal; a temperature detector configured to detect a temperature change above a critical value in an area including the local oscillator; an obtaining module configured to obtain a second clock signal; a clock generator configured to generate the system clock signal in a first manner, using the first clock signal, in a normal mode when the temperature detector does not detect a temperature change above the critical value, and in a second manner different from the first manner, using the second clock signal, in a reverse hold-over mode when the temperature detector has detected a temperature change above the critical value.

System for producing a system clock and temperature gradient detection system

For checking transfer of data cells in an asynchronous switching arrangement, cells are cyclically marked and counted before entering and after leaving the arrangement. A periodical time frame composed of N interleaved checking cycles is imposed. Each cycle (C) includes two phases, a first phase (IC) for marking and counting the cells, when received and before switching, and a second counting phase (OC) for counting cells after switching. An identification mark is introduced in every cell received during the first phase of every cycle, it is linked to the position of this cycle in the time frame. Cells marked according to a cycle are counted as soon as switched during the second phase of the cycle, which starts with a determined delay (d) during each first phase, for a determined duration (t). A determination of the correspondence between the two counts obtained during a cycle is made and induces a fault signaling as soon as such a correspondence as otherwise determined is not obtained.

Method for checking the transfer of data cells in an asynchronous switching arrangement, elementary switching unit and network equipped for such a method

A packetizer arrangement is disclosed with at least one packetizer device (PDPI1..PDPIM, PDPO1..PDPOM) for generating packets of respective individual packet streams from corresponding respective individual data streams (IDS1..IDSN) which are multiplexed and form part of an incoming data stream (CDS). Each of the packets includes a set of subsequent data portions of a corresponding respective individual data stream, and a last data portion included in the set is the one incoming substantially a time interval after a packet immediately preceding the present packet has been generated, this time interval corresponding to the length of this packet.

Packetizer arrangement having packetizer control means (OBC) for

An asynchronous switching node is described for distributing cells from an input port (I1, . . . , IN) of a node (ND) to a group of output ports (LG1, . . . , Lgk) thereof. The asynchronous switching node includes switching stages (S1, S2, S3) each having a switching element (S11, . . . , S3N) with inlets (IP1-IPN) and outlets (OP1-OPN). Each switching element (S11, . . . , S3N) has a routing logic circuit (MC1; MC2; RL) for routing one of the cells from one of the inlets (IP1-IPN) of one of the switching element (S11, . . . , S3N) to one of the outlets (OP1-OPN) thereof based on an internal routing label (LGA; SRT) associated with a cell. The switching element (S11, . . . , S3N) uses the internal routing label (LGA; SRT) to identify at least one distribution tree having branches (BR1, . . . , BR6 ) which connect the input port (I1, . . . , IN) with the group of output ports (LG1, . . . , Lgk). The routing logic circuit (MC1; MC2; RL) has a preselection circuit (MB; M; RM) for preselecting under the control of the internal routing label (LGA; SRT) a set of the branches (BR1, . . . , BR6), has a selection circuit (MX; MX'; SEL) for dynamically selecting one of the branches (BR1, . . . , BR6) and has an identifier circuit for identifying a route on a selected outgoing branch (BR1, . . . , BR6) from the one switching element (S11, . . . , S3N).

Asynchronous switching node and routing logic means for a switching

A cell resequencing system is provided for a resequencing section (RS) of a telecommunication network through which cells of communications are transmitted. The resequencing section includes cell switching networks (SN2) having inlets (I2l/I2n/I2N) coupled to inputs (S1l/S1n/S1N) and outlets (N2l/N2m/N2M). The cells are subjected to a first variable time delay. The cell resequencing system (C1l/C1n/C1N, CK1; R2l/R2m/R2M, CK2) includes latches (R2l/R2m/R2M) coupled between the outlets (N2l/N2m/N2M) and the outputs (S2l/S2m/S2M) to subject the cells to a second variable time delay chosen for each cell so the sum of the first and second variable time delay is substantially equal to a predetermined constant time value, which determines the size of the latches (R2l/R2m/R2M). The resequencing section (RS) has two inputs (S1l, S1n/S1N) each coupled to a distinct inlet (I2l/I2n/I2 N) via a distinct transmission link (TLl/TLn/TLN). The cells are subjected to at least a fixed transfer delay (TD) during their transfer from the input (S1l/S1n/S1N) to the outlet (N2l/N2m/N2M). The fixed transfer delay forms part of the first variable time delay. The minimum size of the latches (R2l/R2m/R2M) is determined by a difference between a predetermined constant time value and the fixed transfer delay (TD).

Cell resequencing system for a telecommunication network

A method for reducing the number of bits in a binary word (AI) which represent a series of addresses, called initial addresses, having a first step (E1) which successively extracts from each initial address (AI) at least one bit (C1) with a fixed rank; forms (1) an address called the selection address (AS) from each bit or bits (C1); extracts from each initial address (AI) a series of bits (C3, C6) using a format (M1i) selected from multiple predetermined first formats (M11, M12, M13, M14), as a function of the selection address; forms (2) with this series of bits (C3, C6) a binary word called the first relative address (AV1); and adds this first relative address to an address called the predetermined basic address (AB(M1i)) associated with the format (M1i) selected to determine this first relative address so as to obtain an address called the first reduced address (AT1) having a smaller number of bits than the initial address (AI); and wherein the basic address (AB(M1 i)) associated with the one (M1i) in the first formats, consists of successively considering the first formats; taking 0 for the basic address associated with the first format considered from the first formats; and taking for the value of each basic address associated respectively with the other first formats, the sum of the last basic address determined for the previously considered first formats, and the maximum relative address value which can be obtained using the last previously considered first format incremented by one unit.

Method for reducing the number of bits in a binary word representing a

The packet transfer control arrangement ensures that an information packet transferred from an input to an output of a packet switching network is available in correct form at that output. It includes copying means (SE11/SEmn) located at the input of the network to make copies of the packet to be transferred, routing means (HA11/HAmn; SE11/SEmn) to transfer these copies independently from each other and possibly over at least partly distinct paths from an input to an output of the network and filtering modules (F11/Fmn) to filter out one of the copies at the output of the network.

Packet transfer control arrangement and related method

Communication system including allocating free signalling channels to

A telecommunication system for transmitting cells through switching nodes (N1-3) interconnected by groups (LG12, LG23) of transmission links, each node including an asynchronous switching network (SN1-3) which comprises several switch elements. At least one of these switch elements possesses a routing group possibility whereby the cells are distributed over its outlets and so further over the different transmission links of the link group to which the switching network is connected. This distribution is performed in function of a self-routing tag which is derived from external routing data associated with the cell. At the input ports of either each or only the first switching network (SN1) of the system, the external routing data is translated in a self-routing tag which is for instance added to the header of the cell, while at the output ports of each or of only the last switching network (SN3) of the system respectively, the self-routing tag is removed from this header. Some switch elements possess a multicast possibility whereby the cells are transferred to several outlets thereof and thereby to several link groups to which the switching network is connected.

Growing community of inventors

Borgerhout, Belgium

Bart J Pauwels