Synopsys, Inc.

Atrenta, Inc.

Barsneya Chakrabarti

Mohammad Homayoun Movahed-Ezazi

Mohamed Shaker Sarwary

Paras Mal Jain

Sridhar Gangadharan

Fahim Rahim

Manish Goel

Guillaume Plassan

Hans-Joerg Peter

Hans-Jorg Peter

Mohammed Movahed-Ezazi

Manish Gupta

Chandan Kumar

Sudeep Mondal

Ankit Arora

A method includes: receiving an integrated circuit design; classifying, by the processing device, a signal path of a sub-circuit of the integrated circuit design based on a connection between an input port of the signal path and a component of the sub-circuit to generate a classification of the signal path; computing, by the processing device, a security vulnerability result of the sub-circuit of the integrated circuit design based on the classification of the signal path and based on a trust level of a zone in a fan-in cone to an input port of the signal path; and generating a security vulnerability report based on the security vulnerability result of the sub-circuit of the integrated circuit design.

Hardware security checks in static verification of integrated circuit designs

Formal verification techniques are used to extract valid clock modes from a hardware description of the clock network. In one aspect, the clock network includes primary clocks and configuration signals as inputs, and also includes derived clocks within the clock network. The derived clocks are configurable for different clock modes according to the values of the configuration signals. A parametric liveness property checking is applied to the derived clocks, where the configuration signals are parameters for the parametric liveness property checking. The parametric liveness property checking infers which values of the configuration signals result in valid clock modes for the derived clocks.

Formal clock network analysis, visualization, verification and generation

A system and method use reactive initialization to facilitate formal verification of an electronic logic design. The system verifies that a part of the logic design correctly transitions through a sequence of states by automatically assigning an initial state value. The system interacts with a correction-unit to provide meaningful feedback of verification failures, making it possible for the correction-unit to correct the failures or add new constraints that allow the verification to complete. Assigning an initial state simplifies the verification of the validity of the remaining states in the sequence, thus making it more likely to reach a conclusive result and consuming less computing resources.

System and method for reactive initialization based formal verification of electronic logic design

A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

Method and apparatus using formal methods for checking generated-clock timing definitions

A system, such as a computer aided design (CAD) system, is configured to abstract at least a portion of an integrated circuit (IC) design provided thereto. The system selects two signals of the IC and determines the respective sub-circuits ending at each of the signals, excluding the other sub-circuit when two sub-circuits intersect. It then identifies an intersection of the two sub-circuits and therefore establishes an abstraction therefrom. The abstraction replaces the circuit for verification purposes of the IC design. The process can repeat as may be necessary or until no two signals have sub-circuits that intersect. The process described for two signals is equally applicable to a plurality of signals for which the intersection is defined as the intersection of all the sub-circuits defined by the plurality signals. The abstraction allows for effective verification of portions of ICs as may be necessary.

System and method for abstraction of a circuit portion of an integrated circuit

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Noida, India

Barsneya Chakrabarti