Nexperia B.v.

Barry Wynne

Yan Lai

Mark Andrzej Gajda

Jan Sonsky

Steven Thomas Peake

Philip Rutter

Phil Rutter

Mark Gajda

The present disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage and the clamping diode defines a second breakdown voltage, with the first breakdown voltage being greater than the second breakdown voltage so that the clamp diode is configured and arranged to receive a low avalanche current and the MOSFET is configured and arranged to receive a high avalanche current.

Semiconductor device with integrated clamp diode

A semiconductor arrangement comprising; a normally-on transistor having first and second main terminals and a control terminal, a normally-off transistor having first and second main terminals and a control terminal, the transistors connected in a cascode arrangement by a connection between one of the main terminals of the normally-on transistor and one of the main terminals of the normally-off transistor, a current-source arrangement connected to a node on the connection and configured to provide for control of the voltage at said node between the normally-on and normally-off transistors by providing for a predetermined current flow, wherein the semiconductor arrangement comprises a first semiconductor die of III-V semiconductor type having the normally-on transistor formed therein and a second semiconductor die having the normally-off transistor formed therein, the current-source arrangement formed in the first and/or second semiconductor dies.

Apparatus and associated method

A semiconductor arrangement comprising; a die of III-V semiconductor material; a resistor element integrated in the die, the resistor element comprising a track defined by a first implant material in the III-V semiconductor material of the die, said track electrically isolated from substantially the remainder of the die by an isolation region that surrounds the track.

Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.

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Glossop, United Kingdom

Barry Wynne