Integrated Device Technology, Inc.

Nortel Networks Corporation

Tundra Semiconductor Corporation

Barry Wood

Mohammad Shahanshah Akhter

Brian Neil Baker

Stephen Routliffe

Victor Menasce

Randy May

Huaiqi Xu

Low Latency Interconnect Integrated Event Handling has been disclosed. In one implementation a hardware based interrupt controller coupled with a hardware based event queue manager, dedicated hardware based queues, and processor instruction extensions allows for off-loading event processing from an operating system thereby dramatically lowering wasted processor cycles while speeding up event processing.

Low latency interconnect integrated event handling

The present invention provides a RapidIO device that includes a switch fabric and a port coupled to the switch fabric. The port is configured to establish a LP-Serial link with RapidIO endpoints, add packet headers having the same acknowledgement identifier to a plurality of contiguous packets and generate a link cyclical redundancy check value for the plurality of contiguous packets having the same acknowledgement identifier, the link cyclical redundancy check code computed to include the value of an acknowledgement identifier header. The port is configured to sequentially output the plurality of packets having the same acknowledgement identifier on the LP-Serial link. In addition, methods are disclosed for formatting bit streams in a RapidIO based communication system and communicating RapidIO packets.

Long-distance RapidIO packet delivery

A Method and Apparatus for Channel Equalization in High Speed S-RIO based Communication Systems have been disclosed. By adjusting equalizer coefficients based on 8B10B error counts and an error threshold, a receiver may be dynamically adjusted. By adjusting transmitter pre-emphasis based on 8B10B error counts and an error threshold, a transmitter may be dynamically adjusted. Both the transmitter and receiver may be adjusted dynamically based on 8B10B error counts and different error thresholds.

Method and apparatus for channel equalization in high speed S-RIO based communication systems

A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to each data source, and to increase functionality while respecting advantageous system characteristics. Fabric output buffers include an arbitration function, a quality of service function, and are associated with individual routing tables. The system uses shallow logic that allows for single clock cycle operation even at high clock speeds. In order to provide for system control of bandwidth, sources with bandwidth practices counter to system interests are addressed. Where there is a conflict of sources over a resource, the buffer management system arbitrates traffic to resolve conflicts in a timely manner while fairly allocating traffic share using a weighted round robin arbitration scheme.

Buffer management in packet switched fabric devices

The present invention relates to a method and apparatus for ensuring fault detection and system recovery in a multiprocessor computing system. This system comprises a multitude of processing element modules, input/output processor modules and shared memory modules. Each module within the system includes an identical period sanity timer capable to reset the module once a predetermined limit count is reached. If a global clear signal is not received from the operating system scheduler by all modules prior to the expiry of the sanity timers, a system-wide reset is effected. Each processing element module within the system further includes a watchdog timer capable to reset the module once a predetermined limit count is reached. If a process is not run by the operating system scheduler on the processing element before the expiry of the watchdog timer, effectively clearing the watchdog timer, the processing element is reset and removed from service.

Growing community of inventors

Dunrobin, Canada

Barry Wood