Motorola Corporation

Barry W Herold

Grazyna A Pajunen

Raymond Louis Barrett

Raymond L Barrett, Jr

Omid Tahernia

Walter L Davis

Scott R Humphreys

Richard Alexander Erhart

Wendell L Little

Joan S DeLuca

Kevin T McLaughlin

Austin Vincent Harton

Francisco Castro

Kenneth R Burch

James G Mittel

Gary L Pace

John Wayne Simmons

Darrell Eugene Davis

Phillip A Johnson

Jeannie Han Kosiec

King F Lee

Mario A Rivas

Bei Tang

Victoria A Leonardo

Jeff LaVell

Robert M Dyas

Zhong Kai Zhong

Margaret Graham-Meighan

Lawrence L Case

Omid Tanernia

James E Berry

Grazyna Anna Pajunen

A photodetector () generates an electrical signal that has a value that changes approximately linearly at a rate that is proportional to an amount of light intensity incident on a photodetector since a most recent reset command was received at a reset input of the photodetector. A measurement circuit () generates a comparison state that is based on a comparison of the value of the photodetector signal to a reference signal in response to one of a plurality a sample pulses. A control circuit () generates the plurality of sample pulses at non-uniform time intervals and generates an elapsed time as an accumulation of the non-uniform time intervals occurring from the reset command to a change of the comparison state. In one embodiment, the reciprocal of an accumulated duration of the non-uniform time intervals is a linear function of a number of time intervals after the reset command.

Light sensing pixel sensor and method

An anti-blooming charge accumulation pixel using an anti-blooming element coupled to the pixel prevents blooming by ensuring that a voltage of a charge accumulation device of the pixel is always returned to a clamping voltage following comparison events. The anti-blooming element is used to return the voltage across a photodiode to the supply voltage when both a low voltage comparison and a high voltage comparison have occurred. A control block is used to determine an input signal to the anti-blooming element based upon the result of a low voltage comparison and a high voltage comparison. The input signal can be used to drive the anti-blooming element to a desired logic level, thereby causing the voltage across the charge accumulation device to be the clamping voltage. The use of the anti-blooming element eliminates blooming to adjacent pixels, independent of an integration time of the pixel.

Digital pixel sensor with anti-blooming control

A pixel image sensor having an array of pixel elements arranged in a color mosaic pattern, each pixel element being responsive to light of a particular color. Each pixel element is supplied with a reference voltage signal corresponding to the color of light to which the pixel element is responsive. The reference voltage signal determined the sensitivity of the pixel element. The white balance of the image sensor is adjusted by varying independently the reference voltage signals for each color. The color mosaic pattern of the array may include a pixel element responsive to white light. The output from the white pixel sensors may be used to adjust the color constancy of the image sensor. The image array reduces the need for post-capture processing of the image for white balancing, by incorporating the white balance operation into the capture process.

Digital pixel image sensor with independent color channel reference signals

A time-integrating pixel sensor having a photo-detector, a capacitor, a comparator and a pixel data buffer. In operation, the photo-current from the photo-detector charges the capacitor and produces a photo-voltage. The photo-voltage sensed by the capacitor and a reference voltage is compared with the comparator. If the photo-voltage exceeds the reference voltage, a global code value is latched into the pixel data buffer. The optical power falling on the photo-detector is determined from the latched code value. An array of sensors is incorporated into a semiconductor device together with circuitry to read and decode the pixel data buffers. The reference voltage may be varied in time to increase the dynamic range of the sensor.

Time integrating pixel sensor

A circuit ( ) for generating a ratio signal indicating a ratio of frequency error to signal magnitude of an input signal includes an FM ratio detector ( ) and a sigma-delta analog-to-digital converter ( ). The FM ratio detector ( ) is responsive to the input signal and generates a magnitude signal and an error signal. The magnitude signal is representative of a magnitude of the input signal and the error signal is representative of a frequency error of the input signal relative to a preselected frequency. The sigma-delta analog-to-digital converter ( ), which is responsive to the filtered magnitude signal and the filtered error signal, generates a stream of logic &ldquo;1's&rdquo; and logic &ldquo;0's&rdquo; that are indicative of a ratio of the filtered error signal to the filtered magnitude signal. Thus, the sigma-delta analog-to-digital converter generates the ratio signal ( ).

Sigma delta FM ratio detector

A portable 2-way secure financial messaging unit (,) includes a receiver (,), a selective call decoder (,), a financial transaction processor (,), a main processor (,), and a transmitter (,). A received secure financial transaction message is decoded by the selective call decoder (,) and either passed directly to a financial transaction processor (,) in the secure financial messaging unit or to a smart card to prevent unauthorized access to information contained in the secure financial transaction message. The portable 2-way secure financial messaging unit (,) may originate as well as receive financial transactions.

Portable 2-way wireless financial messaging unit

A selective call receiver (,) includes a radio receiver (,) and a processor (,). The radio receiver includes an antenna (,), a combination circuit (,), a bandpass filter (,), mixers (,), analog-to-digital converters (,), digital mixers (,), a second combination circuit (,), and a digital-to-analog converter (,). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.

Selective call receiver having an apparatus for modifying an analog signal to a digital signal and method therefor

A random number generator includes a sample clock having a sample clock rate, a chaotic oscillator having a characteristic upper frequency, and an output section. The chaotic oscillator includes a quantized linear section and a non-linear section. The quantized linear section includes multiple quantized integrators coupled to the sample clock and intercoupled in a linear intercoupling. The non-linear section is coupled in a feedback manner with the quantized linear section. The output section generates a random binary output signal having the sample clock rate, formed by a logical combination of binary signals, of which one binary signal is generated by each of the multiple quantized integrators. Each quantized integrator includes an analog to digital converter that preferably includes a sigma delta converter that generates one of the binary signals.

Binary random number generator

A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.

Low power precision current reference

A low input prescaler (800) that is responsive to input signals having low amplitude alternating current (AC) components includes a switched tunable prescaler (280) that generates a prescaler output signal (221) having a prescaler output frequency during an operational state of the prescaler and having a free-running frequency that is responsive to a tuning control signal (216) during a tuning state of the prescaler. A frequency comparator (235) generates a comparator output in response to a difference between a reference frequency and the prescaler output frequency. A prescaler tuner (290, 390) adjusts the tuning control signal in response to the comparator output during the tuning state to minimize the difference between the reference frequency and the prescaler output frequency, and holds the tuning control signal during the operational state. The prescaler is used in phase lock loops (200, 400, 600) and other circuits.

Frequency prescaler method and apparatus responsive to low input drive

A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.

Low power precision voltage splitter

A method and apparatus for frequency synthesis replaces a conventional divide-by-N counter with a low-power binary ripple counter (108). The method and apparatus employs a difference comparison scheme (114) that provides arbitrarily precise channel spacing, and allows loop sample rate to be selected independent of channel spacing.

Method and apparatus for frequency synthesis

A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).

Method and apparatus for extending an operating frequency range of an

A resistorless amplifier circuit uses integrated operational transconductance amplifiers to realize a plurality of circuit transfer functions. The preferred embodiment produces an output signal voltage V.sub.out (500) that is either g.sub.m1 /g.sub.m3 or g.sub.m1 /(g.sub.m3 -g.sub.m1) times the input signal voltage V.sub.in (400). Additionally, an alternative embodiment implements a resistorless summing and subtracting operational transconductance amplifier circuit that realizes an output signal voltage as follows: ##EQU1## The resistorless amplifier circuit includes a first operational transconductance amplifier (100) with a transconductance g.sub.m1, a second operational transconductance amplifier (200) with a transconductance g.sub.m2, and a third operational transconductance amplifier (300) with a transconductance g.sub.m3.

Resistorless operational transconductance amplifier circuit

A low power, fast starting oscillator (10) of the Colpitts type includes an amplifier (12) that provides voltage gain and feeds a source follower circuit (14) that provides a desirable output impedance. A crystal (16) is coupled from an output of the source follower circuit (14) back to the amplifier's input (32). The voltage gain of the amplifier (12) and the output impedance of the source follower circuit (14) are independently selectable to provide an optimum transconductance for the oscillator (10) to start quickly. When oscillations reach a threshold value, the transconductance may be reduced to save power.

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Boca Raton, FL, United States of America

Barry W Herold