Bay Microsystems, Inc.

Barry T Lee

Man Dieu Trinh

Simon S Chong

Goichiro Ono

Charles F Gershman

Jun-Wen Tsong

Steve C Chen

Tony J Chiang

Ryzsard Bleszynski

Eric K Yang

Ryszard Bleszynski

Golchiro Ono

A network processor for processing information elements is described. Each information element is associated with a flow and comprises at least one information element segment. A policy controller stores an information element into at least one information segment storage unit within a memory, and determines whether an information element segment conforms to a predetermined quality of service ('QoS'). A traffic processor selects the information element segment for forwarding based on at least one QoS parameter. A forwarding processor forwards the selected information element segment to an egress port.

Network processor architecture

A differentiated services device is described. In one embodiment, the differentiated services device includes: a traffic metering unit to indicate whether an information element in a flow conforms to a peak rate and a committed rate; a storage congestion metering unit to determine whether the information element should be accepted or discarded; and a marking unit to mark the information element with one of a plurality of mark values, wherein the marking unit is coupled to the traffic metering unit and the storage congestion metering unit. Also, a method of marking an information element in a flow is described. In one embodiment, the method includes: indicating whether the information element in the flow conforms to a peak rate and a committed rate; determining whether the information element should be accepted or discarded; and marking the information element with one of a plurality of mark values.

Differentiated services for a network processor

An embodiment of this invention pertains to a network processor that processes incoming information element segments at very high data rates due, in part, to the fact that the processor is deterministic (i.e., the time to complete a process is known) and that it employs a pipelined 'multiple instruction single date' ('MISD') architecture. This MISD architecture is triggered by the arrival of the incoming information element segment. Each process is provided dedicated registers thus eliminating context switches. The pipeline, the instructions fetched, and the incoming information element segment are very long in length. The network processor includes a MISD processor that performs policy control functions such as network traffic policing, buffer allocation and management, protocol modification, timer rollover recovery, an aging mechanism to discard idle flows, and segmentation and reassembly of incoming information elements.

Vertical instruction and data processing in a network processor architecture

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Union City, CA, United States of America

Barry T Lee