General Electric Company

Barry Scott Whitmore

Robert J Wojnarowski

Bernard Gorowitz

William P Kornrumpf

Raymond Albert Fillion

Charles S Korman

Albert Andreas Maria Esser

A light source includes a substrate; an array of un-packaged light emitting semiconductor devices (LESDs), each of the LESDs having at least one surface for emitting light and a substrate surface being attached to the substrate; and a plurality of electrical connections, each electrical connection coupled for providing electrical power to a respective LESD. The LESDs are arranged on the substrate with sufficient density and light generating capability to provide a predetermined irradiation from the light source.

Light source including an array of light emitting semiconductor devices and control method

A power semiconductor device package includes at least one power semiconductor device mounted onto at least one electrically and thermally conductive spacer having an upper end surface bonded to a back surface of the device; a substrate of hardened substrate molding material surrounding the semiconductor device and the spacer except for an active major surface of the device and an lower end surface of the spacer, a dielectric film overlying the device active major surface and a top side of the substrate, the dielectric layer having a plurality of holes aligned with predetermined ones of the contact pads; a top side patterned metal layer on the dielectric film including portions extending into the holes electrically and thermally connected to contact pads of the device; and a backside metal layer on a substrate bottom side electrically and thermally connected to the spacer lower end surface. Optional through-post structures can be employed to bring all electrical connections either to the top side of the device package or the bottom side. Optional heat sinks can be mounted to the top side, the bottom side, or both sides.

Power overlay chip scale packages for discrete power devices

An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole. A conductive contact area interface may include an electrically conductive first contact area; an electrically conductive second contact area facing and being substantially aligned with the first contact area; and at least one interface structure coupled between the first and second contact areas and including an electrical conductor having a partially open interior to form a compliant joint between the first and second contact areas.

Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas

Interface structures for electronic devices

Growing community of inventors

Waterford, NY, United States of America

Barry Scott Whitmore