Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Geospace Technologies Corporation

Hewlett Packard Enterprise Development LP

Barry S Basile

Alan L Goodrum

Hubert E Brinkmann

David L Matthews

Roger E Tipley

James Michael Hallaman

Robbin Barnet Adams

Ronny Raborn

Danny Sheen

Samuel Anil Choudhari

Roy James

Paul R Culley

David F Heinrich

Brian T Purcell

Paul V Brownell

Raymond Y Chow

Kevin G Depew

David W Engler

Brian V Belmont

Chi Kim Sides

B Tod Cox

William F Whiteman

Arthur G Volkmann

John M Cagle

Binh Nguyen

Philip James McKenzie

Clarence Y Mar

Pamela M Cook

Richard O Waldorf

Paul V Brownnell

Paul V Brownall

William F Doss

Hubert E Brinkmann, Jr

Steve L Radabaugh

Saimak Tavallaei

A seismic data acquisition unit includes a housing, and disposed within the housing, communication circuitry, and circuitry configured to detect and digitize seismic signals. The communication circuitry includes a first transmitter plate, a second transmitter plate, a first receiver plate, a second receiver plate, and a driver. The first and second transmitter plates, and first and second receiver plates, are adjacent a wall of the housing. The driver is coupled to the first transmitter plate and the second transmitter plate. The receiver is coupled to the first receiver plate and the second receiver plate. The communication circuitry transmits digitized seismic signals via a first capacitor that includes the first transmitter plate, and a second capacitor that includes the second transmitter plate. The communication circuitry receives information via a third capacitor that includes the first receiver plate, and a fourth capacitor that includes the second receiver plate.

Systems and methods for seismic data acquisition

A seismic data acquisition unit includes circuitry to detect and digitize a seismic signal, and timing circuitry to control a time of acquisition of each sample of the seismic signal. The timing circuitry include a voltage controlled oscillator (VCO), a local clock incremented by the VCO, and a reference time receiver. The timing circuitry powers on the reference time receiver to generate a reference time value based on signals received from a reference time source, and measures time deviation of the local clock from the reference time value. The timing circuitry determines an adjustment value to apply to the VCO over a time interval during which the reference time receiver is not powered on. The adjustment value is selected to gradually bring the local clock into synchronization with the reference time source over the time interval at a time that the reference time receiver is to be next powered on.

A system for seismic data acquisition includes data recorders that lack external electrical connectors. A seismic data recorder includes a housing. Within the housing the seismic data recorder includes circuitry configured to detect and digitize seismic signals and communication circuitry. The communication circuitry includes a first transmitter plate adjacent a wall of the housing, and a first driver coupled to the first transmitter plate. The communication circuitry configured to communicate the digitized seismic signals to a data retrieval unit that is external to the data acquisition unit via a capacitor formed by the first transmitter plate, the wall of the housing, and a receiver plate external to the housing.

Embodiments provide apparatuses and systems in which slave power sequencers share a command bus and power sequence respective power groups through power sequence states of a power sequencing protocol in response to commands on the command bus. In some examples, a system may include a master power sequencer to output onto a command bus a command to perform a power sequencing protocol for transitioning the system from a first power state to a second power state, and a plurality of slave power sequencers sharing the command bus, each slave power sequencer to power sequence a respective power group to a next power sequence state in response to the command. Other examples are described and claimed.

Power sequencing by slave power sequencers sharing a command bus

A blade server system and method for virtually hot plugging and virtually hot removing functions in a shared I/O environment. A management node physically hot inserts and hot removes an I/O node in the server system without a compute node being aware of the hot insert and hot removal. The management node and the compute node create and remove virtual links between the compute node and the virtual functions.

Virtual hot inserting functions in a shared I/O environment

A method and apparatus for host enumeration process. One embodiment of the method provides a bit to indicate to the host whether enumeration process should start or continue. The bit may be set when the shared resource process has been successfully completed, or the bit may be set if too much time has elapsed since the shared resource process has started, or the bit may be set if too much time has elapsed before the shared resource process is started, or the bit may be set if the shared resource process has not been performed successfully, or the bit may be set if the port is open and it is unnecessary to perform the shared resource process.

Method and apparatus for performing a host enumeration process

A method includes providing a bridge device () connected to a host computing device (--) and a peripheral device (---N,-----), the bridge device () being configured to communicatively couple the host device (--) to the peripheral device (---N,-----); and preventing execution of a hardware enumeration process () in the host device (--) until completion of a resource allocation process () in the bridge device ().

Systems and methods of communicatively coupling a host computing device and a peripheral device

A system for transforming a single root input/output virtualization (SR-IOV) function to appear as a legacy function, and a corresponding method includes a switch platform coupled between a legacy host and a SR-IOV-enabled device. The switch platform includes a processor programmed to discern configuration cycles by type and to process the configuration cycles, and one or more local registers that store data related to the configuration cycles.

System and method for transforming PCIe SR-IOV functions to appear as legacy functions

A server is capable of maintaining a power budget. The server comprises a central processing unit (CPU), a management processor, a power measurement circuit, and a comparison circuit. The comparison circuit receives real time power measurements from the power measurement circuit. A register includes a power budget value from the management processor. The management processor selects a system power performance state for the CPU that utilizes a level of power approximately equal to the power budget value.

Maintaining a power budget

A method determines actual power consumption for system power performance states (SPP-states) of a server. The method comprises initializing the server, performing a worst case workload test, measuring power consumption of the server at one or more SPP-states, and adjusting values in a lookup table to reflect the measured power consumption of the server.

Determining actual power consumption for system power performance states

A system and method for connecting electrical components. More specifically, a method includes positioning a first set of electrical contacts of a first device opposite from a second set of electrical contacts of a second device, and activating a mechanism configured to rotate the first set of electrical contacts between an engaged position against the second set of electrical contacts and a disengaged position offset from the second set of electrical contacts.

System and method for connecting electronic components

A semiconductor package contains at least one electrically isolated channel. The isolated channel is minimally susceptible to crosstalk from other channels in the package. Specifically, the level of crosstalk that may impinge on the isolated channel is below an acceptable threshold so as to permit the isolated channel to function correctly. The semiconductor package may be a FET switch assembly and the isolated channel may be used for a clock signal to prevent crosstalk contamination caused by the data signals.

Isolated channel in an integrated circuit

In electronic systems, signaling problems frequently occur when a device is driving a signal on a line to an incorrect level at a particular point in time. When production schedules do not permit fixing the defects in the errant device, programmable logic has been employed to work around the problems caused by the defective device. Higher device speeds and increasingly complex bus protocols have made the technique of singly using programmable logic, more difficult to implement. The addition of bidirectional switches integrated with and controlled by programmable logic in a monolithic integrated circuit allows the programmable logic device to respond more quickly while at the same time consuming less printed circuit board space. Additionally, the invention provides for termination of the isolated device and/or signal line stubs.

Integration of bidirectional switches with programmable logic

A method for powering up a removable circuit card when it is inserted into a card slot of a computer system includes providing power and a clock signal to the circuit card. A communication link is electrically coupled to the circuit card after both the power and the clock signal are provided to the circuit card.

Removal and insertion of expansion cards in a computer system

A computer system has a bus, a connector for a circuit card, and a clamp configured to selectively prevent removal of the circuit card from the connector when the clamp is engaged. The computer system has circuitry connected to monitor the engagement status of the clamp and to regulate delivery of power to the connector based on the engagement state of the clamp.

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Houston, TX, United States of America

Barry S Basile