Intel Corporation

Barry R Davis

William T Futral

Scott A Goble

Byron R Gillespie

Elliot D Garbus

Elliott Garbus

Mark A Schmisseur

Bruce A Young

Richard Paul Mackey

Nick G Eskandari

Jeff J McCoskey

An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (IO&#xae;) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the IO protocol without interrupting the host processor which normally resides on the primary PCI bus.

Accessing a primary bus messaging unit from a secondary bus through a PCI bridge

A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data queues are provided in the bus bridge for transfer of data in both directions, and the speed of one of the buses is increased over the speed of the other one of the buses. In one embodiment, the first bus is a PCI bus and the second bus is an internal CPU bus.

Low cost data streaming mechanism

A PCI-to-PCI bridge having a processor configured for performing various routing mode operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are known as &ldquo;programmable decode modes.&rdquo; In one programmable decode mode, private address spaces are defined for allowing two or more devices interconnected to a secondary PCI bus to communicate directly using private transactions. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. Another programmable decode mode is &ldquo;intelligent&rdquo; bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus.

Method and apparatus providing an improved PCI bus system

Method and apparatus for tuning the performance of bridge devices, including PCI-to-PCI bridges as well as PCI local bus bridges (or host bridges). The embodiments of the invention permit a multiple-bus computer system to be tuned in view of the application and the bridge queue sizes. Such applications include those concerned with raw bandwidth (such as disk storage), and those that are sensitive to latency (such as networking and videoconferencing). The embodiments of the invention feature a control register that specifies storage conditions to be met by the read and write queues of the bridge. The programmed storage conditions are trigger points which cause the bridge to transfer data into or remove data from the queues during read and write transactions in order to promote the performance (throughput or latency) desired from the bridge.

Trigger points for performance optimization in bus-to-bus bridges

A PCI-to-PCI having programmable decode modes comprising at least one of a standard bridge data transfer transaction, an intelligent bridge data transfer transaction, and a private address space data transfer transaction, and wherein the transactions are configured to bypass a host bus.

Method and apparatus providing programmable decode modes for secondary PCI bus interfaces

A message unit that provides a hardware queue interface between a host processor and a local processor handling I/O operations in an I/O platform. Circuitry manages the head and tail pointers of an inbound free queue, an inbound post queue, an outbound free queue and an outbound post queue. Circuitry is also provided for enabling a host processor or bus agent to access these queues in a single bus transaction by reading or writing inbound port registers or outbound port registers. The queue elements contain handles of message buffers. The invention automatically performs the specific task of locating the next element in a queue, altering that element, and modifying a queue descriptor (i.e., a head or a tail pointer) to indicate the next element for a next queue access. A plurality of registers are used for selectively interrupting either the host processor or the local processor when the queues are written to by either the host processor, a bus agent, or the local processor.

Method and apparatus for transporting messages between processors in a

A method for providing a base address register in a computer system that allows the length of the base address portion of an address to be changed and thereby allows various sizes of address spaces to be supported by the same base address register. The method employs steps that enable and disable bits of the base address register to properly support the desired address space size. Some embodiments of the method set disabled bits of the base address register to a known value. An apparatus that employs the method includes a second register connected to the base address register to supply signals that enable and disable bits of the base address register appropriately.

Apparatus and method for a base address register on a computer

An integrated circuit for providing multiple configuration modes in a multi-funtion intelligent bridge that includes an integrated processor. A first circuit, coupled to a first external bus, for selectively generating retry cycles onto the first external bus in response to a retry signal is provided. A second circuit, coupled to a local processor, for selectively resetting a local processor that is integrated in the intelligent bridge in response to a reset signal is provided. The first and second circuit, in conjunction with the retry signal and the reset signal, selectively provides one of a multiple number of configuration reset modes for the multi-function intelligent bridge.

Method and apparatus for providing multiple configuration reset modes

A computer system is described having one or more host processors, a host chipset and a input/output (I/O) subsystem. The host processors are connected to the host chipset by a host bus. The host chipset is connected to the input/output subsystem by a primary personal computer interface (PCI) bus. The I/O subsystem is connected to I/O devices by a secondary PCI bus. The I/O subsystem includes advanced programmable interrupt controller (APIC) functionality typically provided within an I/O APIC chip within a host chipset. The APIC functionality of the I/O subsystem is primarily implemented in software executing on a core processor of the I/O subsystem. The software creates and accesses various APIC registers and tables, such as a redirection table, within a memory of the I/O subsystem. A single 3-wire APIC bus interconnects the host processors with the I/O subsystem. With this arrangement, non-PCI interrupt lines from the I/O devices are connected only into the I/O subsystem, rather than into the host chipset.

Input/output subsystem having an integrated advanced programmable

An apparatus having a first interface for coupling to a first component bus; a second interface for coupling to a second component bus; an address translation unit coupled to the second interface; and a bus bridge coupled to the first interface and to the second interface. The bus bridge has a first configuration register for disabling an assertion by a first component coupled to the first interface of a component select signal on said second interface; a second configuration register for disabling a propagation by the bus bridge of a private address, contained in an address space which is private to the second interface, from the second interface to the first interface, and to disable a response by the bus bridge to the private address sent from the first interface; and a third configuration register in the address translation unit such that the address translation unit will translate the private address to a local system address in a local system address space, and also translate a local system address contained in the local system address space to the private address.

Method and apparatus for enabling intelligent I/O subsystems using PCI

A PCI-to-PCI bridge is described having a processor configured for performing various routing operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing modes operate on decoded PCI addresses and are described herein as 'programmable decode modes.' In one programmable decode mode, private address spaces facilitate communication between peer PCI devices without burdening the primary PCI bus or any upstream components such as a host-to-PCI bridge, a host bus and host microprocessors. In another programmable decode mode, subtractive routing operations are provided wherein a secondary PCI interface captures any transactions not claimed on the secondary PCI bus after a predetermined number of clock cycles. The transactions are routed to the primary PCI bus. Another programmable decode mode is 'intelligent' bridging wherein conventional inverse positive decode operations are disabled for the entire primary address space of the secondary PCI bus. Only addresses within programmable reverse positive decode address spaces are captured by the secondary PCI interface and forwarded to the corresponding primary PCI bus. Intelligent bridging allows, among other functions, the interconnection of two peer primary PCI buses by a single PCI-to-PCI bridge. Such enables transactions between PCI devices of the peer PCI buses to be routed over the PCI-to-PCI bridge without requiring routing through a host bus.

Method and apparatus providing programmable decode modes for secondary

A processor for creating an intelligent input/output subsystems which includes a local processor coupled to a local system bus; a local memory controller coupled to the local system bus that enables access to a memory from the local system bus; a bus bridge having a first bus interface coupled to a first component bus; a second bus interface coupled to a second component bus, the bus bridge including means for creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; and address translation means coupled to the local system bus and the bus bridge for translating addresses between the local system bus and the second component bus. A method for creating private devices comprising the steps of configuring the bus bridge to disable the assertion by the first component of a component select signal on the second component bus; creating an address space which is private to the secondary component bus such that the bridge will not send any address found in the private address space upstream to the primary component bus; translating the private address to a local system address in a local system address space; and translating a local system address contained in the local system address space to the private address.

Growing community of inventors

Portland, OR, United States of America

Barry R Davis