International Business Machines Corporation

Globalfoundries Inc.

Barry P Linder

Keith Aelwyn Jenkins

Vijay Narayanan

Bruce Bennett Doris

Vamsi Krishna Paruchuri

Takashi Ando

Eduard Albert Cartier

Baozhen Li

Michael Patrick Chudzik

Young-hee Kim

Jason Scott Orcutt

Martin Michael Frank

Shahab Siddiqui

Andrew Tae Kim

James H Stathis

Kevin Geoffrey Stawiasz

Chih-Chao Yang

Hemanth Jagannathan

Rajarao Jammy

Ernest Y Wu

Peilin Song

Franco Stellari

Paul Charles Jamison

Matthew Warren Copel

Chen-Yong Cher

Emmanuel Yashchin

Alan Weger

Michelle Leigh Steen

Min Dai

Raphael Peter Robertazzi

Emily A Ray

Karthik Balakrishnan

Kevin K Chan

Keith Kwong Hon Wong

Karthick Rajamani

Ramachandran Muralidhar

Huiming Bu

Evgeni Petrovich Gousev

Jin Cai

Charles Robert Lefurgy

Malcolm Scott Allen-Ware

Alessandro Cesare Callegari

Alan J Drake

Rishikesh Krishnan

Joseph Francis Shepard, Jr

Claude Ortolland

Young-Hee Kim

Ronald Jay Bolam

Kai Zhao

Steven W Mittl

David F Hilscher

Ghavam G Shahidi

Ruqiang Bao

Ravikumar Ramachandran

Renee Tong Mo

Robert H Dennard

Griselda Bonilla

Sufi Zafar

Tze-Chiang Chen

Robert Daniel Clark

Dae-Gyu Park

John Christopher Arnold

Jae-Joon Kim

Cory Wajda

Manjul Bhushan

Michael Abramovich Gribelyuk

Gert J Leusink

Aditya Bansal

Marinus Hopstaken

Glenn A Biery

Roger Aime Dufresne

Joseph S Newbury

Steven Consiglio

Elnatan Mataev

David G Brochu, Jr

Pierce I Chuang

Robert H Dannard

Shintaro Aoyama

Mathew W Copel

Bruce B Ibm United Kingdom Ltd Doris

Rajarao c/o Ibm United Kingdom Ltd Jammy

A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

Gate stacks with multiple high-κ dielectric layers

A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

RRAM structures in the BEOL

A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

Fabrication of phase change memory cell in integrated circuit

A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit.

Switchable metal insulator metal capacitor

Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.

Detection of performance degradation in integrated circuits

Methods and systems for measuring degradation includes measuring an initial electrical characteristic of a test device in a ring oscillator that includes multiple oscillator stages and a test stage having a delay stage and the test device. The ring oscillator is operated for a period of time. The electrical characteristic of the test device is measured after operating the ring oscillator. A level of degradation in the test device is determined using a processor based on the measurements of the electrical characteristic of the test device.

Measuring individual device degradation in CMOS circuits

Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

BTI degradation test circuit

A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

Dynamic predictor of semiconductor lifetime limits

A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.

Analytics to determine customer satisfaction

A complementary metal-oxide semiconductor (CMOS) circuit and a method of fabricating the device are described. The circuit includes an n-channel field effect transistor (nFET), the nFET including a high-k dielectric layer on an interlayer. The CMOS circuit also includes a p-channel field effect transistor (pFET), the pFET including the high-k dielectric layer on the interlayer and additionally including an aluminum-based cap layer between the high-k dielectric layer and a pFET work function setting metal. Metal atoms from the cap layer do not intermix with the interlayer.

Reduction of negative bias temperature instability

Methods and systems for reducing dark current in a photodiode include heating a photodiode and applying an increasing reverse bias voltage to the heated photodiode to reduce a dark current generated by the photodiode.

Reducing dark current in germanium photodiodes by electrical over-stress

A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.

Non-destructive analysis to determine use history of processor

A method for gaining access beyond a restricted access gateway includes an access key sequence stored on memory of a device. The access key sequence includes a sequence of key entries and key touch movements. An entered request sequence including keys activated by touch on a keyboard of the device and directions of touch movements made on the keyboard is recorded. With an access controller, it is determined whether the recorded entered request sequence matches the access key sequence. Access beyond the restricted access gateway is granted to functions when the recorded entered request sequence matches the access key sequence.

Touch movement activation for gaining access beyond a restricted access gateway

Methods and circuits for monitoring circuit degradation include measuring degradation in a set of on-chip test oscillators that vary according to a quantity that influences a first type of degradation. A second type of contribution to the measured degradation is determined by extrapolating from the measured degradation for the plurality of test oscillators. The second type of contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the first type of degradation for devices represented by the predetermined value.

On-chip combined hot carrier injection and bias temperature instability monitor

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Hastings-upon-Hudson, NY, United States of America

Barry P Linder