Other

C-sierra, Inc.

Barry Moss

James Au

Denis Beaudoin

A system for processing sub-blocks of a macroblock of a video frame. In an example embodiment, the system includes a first module that is adapted to process each sub-block of the macroblock, wherein each sub-block is associated with a predetermined position in a first sequence. The processing of certain sub-blocks in the first sequence requires results of processing of one or more previously processed sub-blocks in the first sequence. A controller selectively enables the first module to process each sub-block of a second sequence that is altered from the first sequence so that the first module implements parallel or pipelined processing of certain sub-blocks of the macroblock. In a more specific embodiment each sub-block in the first sequence of sub-blocks is consecutively numbered 0-15 according to H.264 standards.

Intra-macroblock video processing

A system for selectively handling information. In an example embodiment, the system includes a first mechanism for processing information pertaining to one or more sub-blocks of a macroblock in a first stream and a second stream, and outputting a first processed stream and a second processed stream in response thereto. A second mechanism selectively combines information in the first processed stream and the second processed stream and provides an updated version of the first stream or the second stream to the first mechanism in response thereto. In a more specific embodiment, the first mechanism includes a processor, such as in intra 4&#xd7;4 search, module, that processes a sub-block of a macroblock by performing intra prediction for the sub-block. The processor is adapted to process sub-blocks of a macroblock in parallel, such as in a pipelined fashion or via separate engines capable of operating in parallel.

Selective information handling for video processing

The egress queue manager implements egress port scheduling using positional based storage in a memory array, which is more efficient then using FIFO or linked list approaches

Egress port scheduling using memory efficient request storage

An interface device (102) and corresponding method for coupling a peripheral controller (117) to a host computer (100), the interface device including an emulated universal asynchronous receiver transmitter (UART) (113) for the host computer. The interface device further includes a plurality of registers (203), preferably a control (215), status (227), and data register, such as a multi-register data buffer (401), corresponding to the registers of a UART, a host computer port (112), preferably compatible with a PCMCIA standard, that includes an address map for the plurality of registers (203), a peripheral controller port (114) providing an address mapped parallel interface to the plurality of registers (203), and control logic (207) for providing status signals, including UART status signals, to the host computer port and to the peripheral controller port. The interface device may further include a pacing circuit (303) for substantially emulating, preferably dependent on a baud rate of the data information, the timing limitations of the UART.

Growing community of inventors

Abbotsford, Canada

Barry Moss