International Business Machines Corporation

Ricoh Company, Ltd.

Infoprintsolutions Company, LLC

Ricoh Production Print Solutions LLC

Globalfoundries Inc.

Barry Marshall Trager

Shmuel Winograd

Martin Aureliano Hassner

Luis Alfonso Lastras-Montano

Patrick James Meaney

Mikel J Stanich

Chai Wah Wu

Kartheek Chandu

Charles Edwin Cox

Paul William Coteus

Warren Edward Maule

Eric Eugene Retter

Dong Chen

Alan G Gara

Todd Edward Takken

Timothy Jay Dell

James A O'Connor

Kenneth Lee Wright

Marc Avery Gollub

Piyush Chunilal Patel

Michael Raymond Trombley

James Anthony Marcella

Tetsuya Tamura

Michael K Gschwind

Valentina Salapura

Christian Jacobi

Michael A Blocksome

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Myron Dale Flickner

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

Robert William Wisniewski

Thomas M Gooding

James Lee Hafner

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Matthias Augustin Blumrich

Sameh W Asaad

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Peng Wu

Brad William Michael

Charles David Wait

Sameer Kumar

Arvind M Patel

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Gerard Vincent Kopcsay

William John Kabelac

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Craig Brian Stunkel

David L Satterfield

Douglas R Miller

Rudolf Adriaan Haring

Amith R Mamidala

Yutaka Sugawara

Kristan D Davis

Jose R Brunheroto

Eldee Stephens

Michael B Mundy

Luiz Carlos Alves

Matthew Roger Ellavsky

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Francesco Rezzi

Gabor J Dozsa

Ruth Janine Poole

Peter Boyle

Brant L Knudson

Ralph E Bellofatto

Norman Christ

Kahn C Evans

William Maupin Stockdell

Brian E Smith

Steven Robert Hetzler

Kyu-hyoun Kim

Viresh Paruthi

Manfred Ernst Schabes

Glenn David Gilda

Arthur J O'Neill

Alexey Y Lvov

William Thomas Flynn

Bertrand Gabillard

Walter Hirt

Ali S El-Zein

Irving G Baysah

Robert J Shadowen

Nyles Heise

Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

Common high and low random bit error correction logic

Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols for the memory modules. A host receives and decodes the ECC symbols and executes error correction operations. The host and the memory modules are coupled by a number of channels.

High efficiency redundant array of independent memory

An embodiment includes a method for use in operating a memory chip, the method comprising: operating the memory chip with an increased burst length relative to a standard burst length of the memory chip; and using the increased burst length to access metadata during a given operation of the memory chip. Another embodiment includes a memory module, comprising a plurality of memory chips, each memory chip being operable with an increased burst length relative to a standard burst length of the memory chip, the increased burst length being used to access metadata during a given operation of the memory module.

Error correction potency improvement via added burst beats in a dram access cycle

Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.

Reduced latency error correction decoding

A memory system includes memory modules having a number of sets of memory devices including data memory devices for data and error correction code (ECC). The ECC memory devices carry ECC symbols in order to facilitate Redundant Array of Independent Memory (RAIM) functionalities for the memory modules. A host receives and decodes the ECC symbols and executes RAIM operations. The host and the memory modules are coupled by a number of channels, one channel per each set of the memory devices.

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A method is disclosed. The method includes generating a halftone screen using a Direct Multi-bit Search Screen Algorithm (DMSSA) to optimize a halftone pattern at each gray level.

Mechanism for generating a hybrid halftone using a DMSSA screen

A method is disclosed. The method includes applying a human visual system (HVS) model to a Continuous Tone Image (CTI) and a initial Half Tone Image (HTI) to generate a perceived CTI and a perceived HTI and computing a change in pixel error for a first pixel by toggling the first pixel with all the possible output states and swapping the first pixel with all neighbor pixels.

Halftone mechanism

A method is disclosed. The method includes estimating a quantity of toner to be used to print a job at a printer by calculating a buildup of toner at edges of data on each page of the print job.

Toner Estimation Mechanism

A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.

System for error decoding with retries and associated methods

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A method is disclosed. The method includes generating a Continuous Tone Image (CTI) with all pixel values same as the first gray level and an initial Half Tone Image (HTI) with all pixel values equal to minimum absorptance level, computing a change in pixel error by toggling with all the possible output states and swapping with all neighbor pixels only if the stacking constraint is satisfied, updating the HTI with the maximum error decrease operation and continue to next pixel location till the end criteria is met. Once the end criteria is met, the updated HTI is saved as a final halftone screen for that gray level and copied as the initial HTI for the next gray level along with CTI pixel values updated to the next gray level till the final gray value is reached.

Halftone screen generation mechanism

A method is disclosed. The method includes generating a Continuous Tone Image (CTI) with all pixel values same as a first gray level, generating an initial Half Tone Image (HTI) with all pixel values equal to minimum absorptance level and computing a change in pixel error for a first pixel. The change in pixel error is computed by identifying a first pixel indicated in a valid pixel map, toggling the first pixel with all the possible output states and swapping the first pixel with all neighbor pixels only if the stacking constraint is satisfied, updating the HTI with the maximum error decrease operation and continue to next pixel location till the end criteria is met.

Hybrid halftone generation mechanism using change in pixel error

A method is disclosed. The method includes generating a set of points via energy minimization to implement halftone seed pattern.

Method and system for halftoning using energy minimization

Growing community of inventors

Yorktown Heights, NY, United States of America

Barry Marshall Trager