Motorola Corporation

Barry M King

Paul Golding

Andrew Page

Irwin Bennett

Mayank Kapadia

Graham Ronald Johnson

A feedback and shift unit is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a particular operating function, such as a linear feedback shift or a stepping function used by encryption algorithms. The feedback and shift unit (50) comprises a linear feedback shift register (52) for storing a value of the feedback and shift unit. A tap register (56) stores a tap position indicator indicative of tap positions for the feedback and shift unit (50). An input provides data to the feedback and shift unit. A feedback matrix, coupled to receive the data from the input, provides data bits, generated in response to the data and the tap position indicator, that are shifted into the linear feedback shift register (52) to form the value stored therein.

Feedback and shift unit

A cyclic redundancy coder (10) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The cyclic redundancy coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a bit of a cyclic redundancy code word. A tap register (16) stores a tap position indicator indicative of tap positions in the cyclic redundancy code word that are subject to a logical operation. An input (18) provides input data to the cyclic redundancy coder. A logic feedback network (20-28) receives the data from the input and provides the logical operation. The logic feedback network also provides a plurality of data bits generated in response to the input data and each bit contained in each storage element identified by the tap position indicator. The cyclic redundancy code word is produced by applying at least one of the plurality of data bits to one storage element that is adjacent a tap position.

Cyclic redundancy coder

A transcoder is described for performing transcoding operations, that is to say coding and decoding operations on voice data arranged over a plurality of voice data channels. It comprises a first interface (10) for inputting and outputting coded voice data, a second interface (11) for inputting and outputting decoded voice data; at least one transcoder processor (101) for performing transcoding operations on voice data arranged over at least two voice data channels; and an input/output processor (100) coupled to the first and second interfaces and the at least one transcoder processor for controlling the flow of data between the first and second interfaces and the at least one transcoder processor. The input/output processors controls the at least one transcoder processor to perform transcoding operations on a selected channel at a given time. The invention is particularly applicable to transcoding between CEPT standard voice data and GSM standard voice data.

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Swindon, United Kingdom

Barry M King