International Business Machines Corporation

Barry Lee Dorfman

Bruce Martin Fleischer

Terry I Chappell

Barbara A Chappell

David J Widiger

Thomas Edward Rosser

Jeffrey Paul Soreff

Gary Stephen Ditlow

Michael P Beakes

Vinod Narayanan

Ghavam G Shahidi

Chandramouli Visweswariah

Kerim Kalafala

Jeffrey G Hemmett

Natesan Venkateswaran

Debjit Sinha

Vasant B Rao

Robert Alan Philhower

Adil Bhanji

Ravichander Ledalla

Fred Lei Yang

George Anthony Halasz

A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net.

Timing point selection for a static timing analysis in the presence of interconnect electrical elements

A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects

A technique for detecting and correcting inaccuracies in curve-fitted models. Humps and dips in a curve-fitted model are identified. An analysis is performed on the humps and dips to determine if they are large enough to warrant correction. If so, then the source of the simulation and/or empirical data is modified to taking corrective action to improve the curve fit between the edge point and the next actual simulation and/or empirical data point.

Method and apparatus for detecting and correcting inaccuracies in curve-fitted models

A computer-based method automatically synthesizes, optimizes and compiles high performance control logic using SRCMOS LOGIC ARRAY MACROS, abbreviated as SLAMs. The method includes a series of steps that transform a high level design description into a set of SLAMs, and includes the steps of partitioning the logic description of a unit into blocks that are suitable for mapping to a target SLAM structure; mapping each logic partition to the target SLAM structure; creating a configuration and relative layout for the internal structure for each SLAM; creating an external description for each SLAM, each description being of sufficient detail to carry out physical design and integration of the unit which contains the SLAM; assembling the partitions implemented as SLAMs with other macros in the unit; resolving interface conflicts between the different macros by selecting appropriate signal interfaces for various SLAMs; repeatedly changing the external specifications of the various SLAMs; analyzing the performance of the unit; automatically compiling the schematic and layout of each SLAM within the unit based on the configuration and relative layout; and assembling the macros and analyzing the design for design rule violations.

Method and apparatus for synthesizing and optimizing control logic based

A logic circuit family implements self-resetting CMOS logic array macros (SLAMs) which include a plurality of inputs to which a plurality of data input signals can be applied; a plurality of input buffers coupled to receive the input signals from the inputs; a NOR circuit coupled to receive the outputs of the input buffers and a pulsed logic timing signal synchronized within a predefined window with the arrival of the data input signals; an output buffer coupled to receive the output of the NOR circuit; and an output at which a data output signal is produced, with the output signal being a logical NOR of the data input signals; and with each of the NOR circuit, the plurality of input buffers, and the output buffer optionally having a separate reset input to reset it to a standby state. The SLAMs address the very high pressure on the performance of both control logic and control logic design systems. The distinguishing features of SLAMs are uniquely combined to allow the automated design, from a logic description and interface specifications, of a complete macro satisfying predetermined design guidelines.

Compiled self-resetting CMOS logic array macros

A system and method for verifying the integrity of files, and in particular executable files on a server workstation in a distributed computing network. In one form, verification is accomplished by selecting random or pseudo-random sections of the file, both as to the location and size, and comparing check code results for those sections with corresponding calculations of check codes for a secure master file. In the context of a network, the objective is to verify the integrity of the executable file, typically located in as unsecure server computer, and once so verified transmit over a relatively secure communication network confidential data to be used by the executable file. The systems and methods for practicing the invention in a distributed computing network involving communication, using relative security protocols, between a dispatcher workstation and a server workstation and resources to generate and compare random or pseudo-random number pairs which define sections of the executable file subject to authentication. The comparison involves check code computations for the sections defined by the number pairs as appears in the server computer file as well as a master executable file in the dispatcher computer. A comparison of the check codes determines the integrity of the executable file in the server computer.

Method and system for authenticating files

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Barry Lee Dorfman