Texas Instruments Corporation

Barry Lanier

Thomas Dyer Bonifield

James Carl Baker

Douglas E Paradis

Julie S England

Emily A Groves

Charles P Monaghan

Glenn A Cerny

Vincent C Korthuis

Mona M Eissa

Basab Chatterjee

Brian E Zinn

Satyavolu Papa Rao

Chad J Kaneshige

Light is incident on a semiconductor wafer polish surface and an adjacent reference surface (). The reflected light from each surface is detected by a detector () positioned beneath the surfaces. The signals derived from each source of reflected light is analyzed in a electronic system () and an endpoint for a chemical mechanical polish process is determined as a function of both signals.

Chemical mechanical polishing optical endpoint detection

A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer. The process also includes the steps of simultaneously buffing a second wafer with the buffing pad for a second length of time, in which the first length of time is greater than the second length of time, and rinsing the buffing pad and the buffed wafer with a moisture maintenance compound for at least a portion of the time between the completion of the second length of time and the first length of time. Moreover, the moisture maintenance compound substantially prevents drying of the buffed wafer between the completion of the second length of time and the first length of time.

Processes for chemical-mechanical polishing of a semiconductor wafer

A hybrid semiconductor device which comprises a semiconductor substrate having electrical devices therein with a plurality of spaced apart relatively rigid standoffs of electrically insulating material disposed over the substrate. Each of the standoffs has a substantially planar exposed surface remote from the substrate. A first layer of electrically insulating material more resilient than the standoffs is disposed over the substrate and between the standoffs and has an upper surface coplanar with the planar exposed surfaces of the standoffs. A semiconductor superstrate is secured to the first layer of electrically insulating material, the superstrate containing electrical devices. A connection connects the electrical devices contained in the superstrate to the electrical devices in the substrate.

Hybrids semiconductor circuit

A method of making a hybrid semiconductor device and the device comprising providing a semiconductor substrate having electrical devices therein, providing a first resilient layer of electrically insulating material over the substrate which can be disposed directly onto the substrate with a substantially planar exposed surface, providing a second resilient layer of electrically insulating material over the first resilient layer which can be disposed directly onto the first layer with a substantially planar exposed surface, the second layer having a relatively resilient state and a rigid state, providing resilient standoff from the third resilient layer at spaced locations on the second layer by removing predetermined portions of the third layer, securing a semiconductor superstrate to the semiconductor device, forming electrical devices on the superstrate, and then connecting the electrical devices on the superstrate to the electrical devices on the substrate.

Semiconductor hybrids and method of making same

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Barry Lanier