Analog Devices,inc.

Globalfoundries Inc.

Transwitch Corporation

Analog Devices Technology

Barry L Stakely

Rodney Dean Miller

William L Bucossi

Jingang Yi

Alexis Shishkoff

Frederick Carnegie Thompson

Jiefeng Yan

Phillip R Epley

Rodney D Miller

Gan Guo

Ernesto Jaritz

Embodiments of the disclosure provide a differential clock duty cycle correction (DCC) circuit, including: a hybrid current injector including current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of a n-bit DAC code to generate the correction current; and a current DAC for receiving a second, different portion of the n-bit DAC code and for outputting a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.

Differential clock duty cycle correction with hybrid current injectors and tapered digital to analog converter

Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.

Use of a DLL to optimize an ADC performance

Apparatus and methods are disclosed, such as those involving a high frequency transmitter. One such apparatus includes a pre-amplifier configured to receive an input signal via an input node; and a capacitor block electrically coupled between the pre-amplifier and an output node from which an output signal is transmitted. The capacitor block is configured to provide charge to the output node or pull charge from the output node while the output signal transitions. The apparatus further includes a switch electrically coupled between the output node and a voltage reference, wherein the switch is turned on or off at least partly in response to a signal from the pre-amplifier. This configuration effectively reduces rise and fall time of the output signal for high-frequency transmission.

Apparatus and method for HDMI transmission

A high-definition multimedia interface circuit uses a high-definition multimedia interface encoder to produce a plurality of channels of data. An output circuit, connected to the high-definition multimedia interface encoder, produces a plurality of channels of high frequency data from the data produced by the high-definition multimedia interface encoder. A multiplexer selects a channel for sampling, and a capacitive coupler capacitively couples the multiplexer to a sampling circuit. The sampling circuit produces sampled data corresponding to the high frequency data having a clock rate less than a clock rate of the high frequency data. A test circuit compares the sampled data with the data produced by the high-definition multimedia interface encoder.

Self-test circuit for high-definition multimedia interface integrated circuits

A phase/frequency detector includes two D-Q flip-flops, an OR gate, and an exclusive NOR (XNOR) gate. The phase/frequency detector is used in conjunction with a clock dejitter PLL where the underflow and overflow flags from a FIFO are coupled to the inputs of the OR gate and the Q outputs of the flip-flops are coupled to the inputs of the XNOR gate. The Qb output of each flip-flop is coupled to the D input of the respective flip-flop. The recovered clock signal is coupled to the clock input of the first flip-flop and the output of the VCXO is coupled to the clock input of the second flip-flop. The SET input of the first flip-flop is coupled to the overflow flag and the RESET input of the first flip-flop is coupled to the underflow flag. The SET input of the second flip-flop is coupled to the output of the OR gate and the output of the XNOR gate is passed through the filter to the input of the VCXO. When the phase is locked, the output of the XNOR has a 50% duty cycle which causes the voltage across the filter to remain constant which maintains a steady VCXO output frequency. The FIFO will either underflow or overflow if the recovered clock and the VCXO run at different speeds. In this case, the flip-flops generate correction pulses that will drive the PLL filter voltage to the point where the VCXO is running at the correct frequency.

Phase/frequency detector for dejitter applications

An apparatus for correcting imperfectly equalized bipolar signals includes a delay line having a reset control, an AND gate, and a one-shot multivibrator. The apparatus is used in conjunction with an adaptive equalizer with the output of the adaptive equalizer being coupled to the input of the apparatus of the invention. More particularly, the output of the equalizer is coupled to the input and reset of the delay as well as to one input of the AND gate. The output of the delay line is coupled to the other input of the AND gate. The output of the AND gate is coupled to the input of the one-shot multivibrator and the output of the one-shot multivibrator is the corrected signal. The delay line is approximately equal to the pulse width of an erroneous pulse which is expected from over-equalization. When the delayed signal is compared to the original signal via the AND gate, narrow pulses are removed from the signal. The one-shot multivibrator is configured such that each pulse entering it from the output of the AND gate cause a pulse of a set length to be generated by the one-shot multivibrator. The output of the one-shot multivibrator therefore contains pulses of equal length. If a pulse from the equalizer is too narrow to be a valid bit, it causes the delay to reset.

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Snow Camp, NC, United States of America

Barry L Stakely