Digital Equipment Corporation

Other

Barry L Rubinson

Edward A Gardner

Richard Franklin Lary

Robert G Bean

Peter T McLean

O Winston Sergeant

Michael E Beckman

David William Thiel

Robert E Willard

Verell Boaen

William Watson

Catharine Van Ingen

Dale R Keck

Robert Blackledge

William A Grace

Mark A Parenti

Michael Chow

A dual addressing arrangement comprises a complex address pointer within entries of a communication queue used by a port driver and an port adapter when exchanging information in a host computer. The complex address pointer comprises a virtual address portion and a physical address portion. The port driver uses the virtual address portion to ascertain the location of entry structures, while the port adapter uses the physical address portion to locate the structures in a host memory. The arrangement and interpretation of the address portions of the complex pointers within an entry depend upon the direction of information flow, i.e., the passing of messages from the port driver to the port adapter using a driver-to adapter queue or the passing of responses from the adapter to the driver using an adapter-to-driver queue.

Dual addressing arrangement for a communications interface architecture

A communication interface between a port driver and an port adapter of a host computer includes a singly-linked queue resident in a host memory of the computer. The queue includes a header element and a stopper element with message entries linked therebetween. The message entries contain information to be exchanged between the port driver and port adapter. Each message entry includes at least a carrier that contains a forward link pointer to the next entry in the queue and message/response specific control information. The stopper element identifies the end of the queue and is distinguishable from a message entry by a valid indicator, e.g., the state of at least one bit of the forward link pointer. Functionally, the stopper entry allows the port driver and port adapter to concurrently insert and remove message entries of the singly-linked queue in a reliable manner without the use of any external synchronization mechanism.

Queue apparatus and mechanics for a communications interface architecture

A memory mapping system for use by a port adapter in a computer facilitates access to named data buffers in host memory. The system generally comprises a mechanism that enables the adapter to efficiently translate the data buffer name to physical address locations in host memory without knowledge of the memory management policies of the computer. Specifically, the system includes various data structures and pointers that allow the port adapter to view host memory in 'port pages' when accessing memory locations of a named data buffer. The data locations are virtually, but not physically, contiguous and the invention provides efficient identification of the physical addresses of the locations.

System for accessing information in a data processing system

A secondary storage facility having a drive and a controller employing multiple error recovery techniques; the controller signals the drive to try such techniques in sequence, according to descending a priori probability of success. The controller does not know or need to know the details of the error recovery procedures.

Secondary storage facility empolying serial communications between drive

In a system including a plurality of mass storage devices at least one of which includes first and second ports, a plurality of controllers and cables coupling the ports to various ones of the controllers and in which each device can only be on-line through one port at a time, state information is sent from the on-line port of each device to a first controller to which it is coupled until a predetermined command from the controller to the on-line port is sent by the first controller. The device responds to the predetermined command by discontinuing the sending of state information from the on-line port to the first controller, and sending a state available signal from the other port to the second controller while maintaining the actual state of said device unchanged, permitting the other controller to interrogate the device as an aid in determining system topology.

Secondary storage facility employing serial communications between drive

In a data processing system including a host computer and a secondary storage system that includes a controller and a mass storage device, the device stores information regarding the physical and logical characteristics of a disk drive associated with the device. In response to a command from the controller, the device produces a signal or signals which provide information to the controller regarding the physical and logical characteristics of the disk drive. The physical and logical characteristics include the drive bit transfer rate and subunit characteristics.

A radial bus for use in a secondary storage subsystem, between a mass storage drive and controller. The bus has four unidirectional bit-serial channels, two for carrying signals from drive to controllers. One channel carries real-time drive state information to the controller; another carries real-time controller state information to the drive. The state information is a sequence of multiplexed bits sent in continuous repetition. Most status variables are represented as a single bit in a specific place in the sequence; the set of status variables defining drive state or controller state, as the case may be, is thus provided by a sequence of bits. When such a bit changes state, a potential change of status has occurred; the change is required to persist some number of repetition of the sequence before the state change is recognized, to avoid spuriously signalling a state change.

A control arrangement for coordinating operations of multiple processors in a multiprocessor system in response to a command. Each command is associated with a route comprising a sequence of route vectors, each identifying an operation to be performed to execute the command, as well as the process, or station, to execute the route vector. In response to the receipt of a command, a control block is generated identifying the first route vector in the route associated with the command. Each station has a work queue containing control blocks, which the station retrieves and processes sequentially. The control block is first sent to the work queue of the station to perform the first operation. When the station gets to the control block, it performs the operation required by the route vector, modifies the control block to identify the next route vector in the sequence, and transfers the control block to the work queue of the station to perform the operation required by the next route vector in the route.

Apparatus and method for controlling digital data processing system

An interface mechanism (10) between two processors, such as a host processor (70) and a processor (31) in an intelligent controller (30) for mass storage devices (40), and utilizing a set of data structures employing a dedicated communications region (80A) in host memory (80). Interprocessor commands and responses are communicated as packets over an I/O bus (60) of the host (70), to and from the communication region (80A), through a pair of ring-type queues (80D) and (80E). The entry of each ring location (e.g., 132, 134, 136, 138) points to another location in the communications region where a command or response is placed. The filling and emptying of ring entries (132-138) is controlled through the use of an `ownership` byte or bit (278) associated with each entry. The ownership bit (278) is placed in a first state when the message source (70 or 31) has filled the entry and in a second state when the entry has been emptied. Each processor keeps track of the rings' status, to prevent the sending of more messages than the rings can hold. These rings permit each processor to operate at its own speed, without creating race conditions and obviate the need for hardware interlock capability on the I/O bus (60).

Interface between a pair of processors, such as host and

In a disk mass storage facility for data processing systems, a disk format which improves handling of defective segments of medium and reduces access time. The format has three layers. A first, physical layer comprises the bytes, sectors and collections of sectors, as well as error detection and correction codes. A second, logical layer is used to address the physical layer and to collect together sectors to form a multiplicity of separately addressable spaces, with each space having a distinct functional utility. At a third, functional layer the use of data fields in each space is specified. This layer governs the handling of bad blocks if required, and the use of certain format information. Handling of bad blocks is controlled by a hierarchically layered process. A portion of each disc, distributed across the medium, is reserved as spare sectors to replace defective sectors. After a bad sector is replaced, future attempts to access the bad sector are redirected (i.e., revectored) to the replacement sector. For the simplest revectoring, the bad block is replaced by a replacement block in a known location. If that cannot be done, multiple copies of the replacement block's header are stored in the bad block's data field and the copies are compared to find the replacement address. If the comparison fails, or the header cannot be read, a back-up table is available to match the available replacement addresses with the original address which was replaced. A special code is used to identify blocks wherein the medium is good but the contents of the block are logically corrupted.

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Colorado Springs, CO, United States of America

Barry L Rubinson