At&t Teletype Corporation

Barry H Jacksier

Gary B Ollendick

An adjustable time delay circuit 10, 50 includes a time delay line 12 including a plurality of series connected time delay units 18a-p. During adjustment, sampled signals along the delay line 12 are compared with a reference signal by NOR-gates 22e-m. Upon a comparison being attained, the output of the corresponding NOR-gate 22e-m sets a selected flip-flop 30e-m which in turn routes the signal at a selected delay line tap 38e-m through a NOR-gate 34e-m to an output OR-gate 40. The tap 38e-m selected, compensates for component propagation characteristics thus maintaining a predetermined time delay through the time delay circuit 10.

Adjustable time delay circuit

A receiver for a biphase-L signal A is described which includes a line-up detector 14 generating a circuit initialization pulse. A preamble detector 40 is responsive to a preamble of the incoming biphase-L signal A. A sampling signal generator 17 is responsive to the signal from the preamble detector 40, to the biphase-L signal A and to a second control signal. The output C of a time delay line 34 supplies the second control signal, and the input to the delay line 34 is supplied by the sampling signal generator 17. The output data signal H is generated by a flip-flop 54 which samples the biphase-L signal A at times determined by the output G of the sampling signal generator 17.

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Wheeling, IL, United States of America

Barry H Jacksier