Massachusetts Institute of Technology

Other

United States of America As Represented by the Secretary of the Air Force

Baylor College of Medicine

Houston Advanced Research Center

Barry E Burke

Bernard B Kosicki

Eugene D Savoye

Daniel J Ehrlich

Robert K Reich

Dennis D Rathman

Mark Alexander Hollis

Michael E Hogan

Richard Hart Mathews

Ernest R Stern

R Allen Murphy

Rajender S Varma

Richard W Ralston

Daniel L Smythe, Jr

Mitch D Eggers

Alice M Chiang

Jonathan C Twichell

Mordechai Rothschild

James E Carrick

William D Goodhue

Allen M Waxman

Kirby B Nichols

James A Gregory

Andrew H Loomis

William T Lindley

James E Landry

Chang-Lee Chen

David A Fay

Alan N Gove

Vyshnavi Suntharalingam

William H McGonagle

Robert W Mountain

Jammy C Huang

John P Doty

George R Ricker, Jr

Gregory Y Prigozhin

John Tonry

An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array. A substrate bulk region between the shutter buried layer and the photogenerated-charge-extinguishment layer is characterized by an electrical resistivity enabling independent electrical bias of the photogenerated-charge-extinguishment layer from electrically-doped regions of the substrate.

Electronic shutter with photogenerated charge extinguishment capability for back-illuminated image sensors

An insulating material and the method of applying the insulating material to products and systems. The material, method and system may be applied to tubulars used in deep water projects. The insulating material is composed of ceramic particles, epoxy and an acrylate monomer that is a precurser to an acrylic resin, and additives. Equal volumes of a epoxy component mixtures and a curing agent component mixture when heated and mixed together create a liquid insulating material that can be applied to the outer surface of pipe involving a repetitive series of steps controlled by an operator at a main control panel. Pipe unrolled from a pipe reel is straightened and heated. In a heated retort, liquid insulating material is applied to the surface of pipe and cured to the final insulation coating. The final coated pipe can be replaced on the reel for shipment to the job site. Within the deep sea environment the hardness of the insulating material can withstand the compressive pressure, water absorption and corrosion; and the insulating properties avoid the affects of near-freezing water temperatures. A curing agent in the formulation provides flexibility to the insulation. In the underwater environment, current movements can damage and breech the connections of the systems. Flexibility in the insulation will protect the systems from the currents and ensure integrity of the systems especially critical in piping systems.

Insulating material of epoxy compound, acrylic resin, ceramic particles and curing agent

In accordance with the invention, an electrically conducting charge transfer channel is formed in a semiconductor substrate and an electrically insulating layer is formed on a surface of the substrate; a layer of gate electrode material is formed on the insulating layer. On the gate material layer is formed a first patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gate electrodes, and the first-pattern-exposed regions of the gate material layer are electrically doped. In addition, on the gate material layer is formed a second patterned masking layer having apertures that expose regions of the underlying gate material layer that are to form gaps between gate electrodes, and the second-pattern-exposed regions of the gate material layer are etched.

High-yield single-level gate charge-coupled device design and fabrication

The CCD image sensor addresses the problem of noise, due to background charge generated by Compton scattering of gamma rays. In applications, in which an imager must operate in a high-radiation environment, such background noise reduces the video signal/noise. This imager reduces the amount of charge collected from Compton events, while giving up very little sensitivity to photons in the visible/near IR.

Image sensor with reduced sensitivity to gamma rays

A charge-coupled device imager including an array of super pixels disposed in a semiconductor substrate having a surface that is accessible to incident illumination. For each super pixel there is provided a plurality of subpixels which each correspond to one in the sequence of image frames. Each subpixel includes a doped photogenerated charge collection channel region opposite the illumination-accessible substrate surface, a charge collection channel region control electrode, doped charge drain regions adjacent to the channel region, a charge drain region control electrode, and a doped charge collection control region. To each subpixel are provided channel region and drain region control voltage connections, for independent collection and storage of photogenerated charge from the substrate at the charge collection channel region of a selected subpixel during one in the sequence of image frames and for drainage of photogenerated charge from the substrate to a drain region.

High-speed, high-sensitivity charge-coupled device with independent pixel control of charge collection and storage

Provided is a method of fabrication of a blooming control structure for an imager. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate. The blooming barrier region is of a conductivity type and level that is selected based on the blooming barrier width to produce a corresponding electrical potential barrier between the charge collection and blooming drain regions. The blooming barrier regions of the structure are very precisely defined by the selected acute blooming barrier impurity implantation angle, and optionally in addition by a rotation of the blooming barrier impurity implantation, as well as a non-vertical sidewall profile of the an impurity implantation masking layer.

Fabrication of a high-precision blooming control structure for an image sensor

An event-driven X-ray CCD imager device uses a floating-gate amplifier or other non-destructive readout device to non-destructively sense a charge level in a charge packet associated with a pixel. The output of the floating-gate amplifier is used to identify each pixel that has a charge level above a predetermined threshold. If the charge level is above a predetermined threshold the charge in the triggering charge packet and in the charge packets from neighboring pixels need to be measured accurately. A charge delay register is included in the event-driven X-ray CCD imager device to enable recovery of the charge packets from neighboring pixels for accurate measurement. When a charge packet reaches the end of the charge delay register, control logic either dumps the charge packet, or steers the charge packet to a charge FIFO to preserve it if the charge packet is determined to be a packet that needs accurate measurement. A floating-diffusion amplifier or other low-noise output stage device, which converts charge level to a voltage level with high precision, provides final measurement of the charge packets. The voltage level is eventually digitized by a high linearity ADC.

Event-driven charge-coupled device design and applications therefor

Provided is a blooming control structure for an imager and a corresponding fabrication method. The structure is produced in a semiconductor substrate in which is configured an electrical charge collection region. The electrical charge collection region is configured to accumulate electrical charge that is photogenerated in the substrate, up to a characteristic charge collection capacity. A blooming drain region is configured in the substrate laterally spaced from the charge collection region. The blooming drain region includes an extended path of a conductivity type and level that are selected for conducting charge in excess of the characteristic charge collection capacity away from the charge collection region. A blooming barrier region is configured in the substrate to be adjacent to and laterally spacing the charge collection and blooming drain regions by a blooming barrier width. This barrier width corresponds to an acute blooming barrier impurity implantation angle with the substrate. The blooming barrier region is of a conductivity type and level that is selected based on the blooming barrier width to produce a corresponding electrical potential barrier between the charge collection and blooming drain regions. This blooming control structure, and particularly the blooming barrier regions of the structure, are very precisely defined by the selected acute blooming barrier impurity implantation angle, and optionally in addition by a rotation of the blooming barrier impurity implantation, as well as a non-vertical sidewall profile of the an impurity implantation masking layer.

High-precision blooming control structure formation for an image sensor

A hybrid integrated circuit and method of fabricating a hybrid integrated circuit. A first wafer is provided having a first surface with a first electrical contact for a first active circuit associated therewith and a second surface. A second wafer is provided having a third surface with a second electrical contact for a second active circuit associated therewith and a fourth surface, the second wafer being chemically thinned at the fourth surface. The first and second wafers are bonded together at an interface between the first and third surfaces such that the first and second electrical contacts are relatively aligned with one another. The fourth surface of the second wafer is processed to define an access via to both the first and second contacts. An electrical interconnection is formed between the first and second contacts within the access via so that the first and second active circuits are electrically interconnected.

Interconnection technique for hybrid integrated devices

An imaging system is provided for imaging a scene to produce a sequence of image frames of the scene at a frame rate, R, of at least about 25 image frames per second. The system includes an optical input port, a charge-coupled imaging device, an analog signal processor, and an analog-to-digital processor (A/D). The A/D digitizes the amplified pixel signal to produce a digital image signal formatted as a sequence of image frames each of a plurality of digital pixel values and having a dynamic range of digital pixel values represented by a number of digital bits, B, where B is greater than 8. A digital image processor is provided for processing digital pixel values in the sequence of image frames to produce an output image frame sequence at the frame rate, R, representative of the imaged scene, with a latency of no more than about 1/R and a dynamic range of image frame pixel values represented by a number of digital bits, D, where D is less than B. The output image frame sequence is characterized by noise-limited resolution of at least a minimum number, N.sub.M, of line pairs per millimeter, referred to the charge-coupled imaging device pixel array, in an imaged scene as a function of illuminance of the input light impinging the charge-coupled imaging device pixels.

Low-light-level imaging and image processing

A method and apparatus are disclosed for identifying molecular structures within a sample substance using a monolithic array of test sites formed on a substrate upon which the sample substance is applied. Each test site includes probes formed therein to bond with a predetermined target molecular structure or structures. A signal is applied to the test sites and certain electrical, mechanical and/or optical properties of the test sites are detected to determine which probes have bonded to an associated target molecular structure.

Optical and electrical methods and apparatus for molecule detection

A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode. The potential pocket is formed by an ion implantation into the semiconductor substrate, a region of an insulating layer having a thickness which differs from the thickness of the remainder of the insulating layer positioned between the gate electrode and the substrate, a second gate electrode positioned adjacent the first gate electrode, or a lightly or undoped second region of a resistive layer disposed adjacent the gate electrode.

Reduction of trapping effects in charge transfer devices

A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

Multidirectional transfer charge-coupled device

A surface electron barrier region is formed on a semiconductor membrane device by a single step laser process which produces a sharp doping profile in a surface region above the light penetration depth. Enhanced quantum efficiency is observed, and by selectively forming barrier layers of differing depth, a CCD device architecture for two-color sensitivity is achieved. The barrier layer results in enhanced membrane-type and radiation hardened bipolar and CMOS devices.

Barrier layer device processing

Growing community of inventors

Lexington, MA, United States of America

Barry E Burke