International Business Machines Corporation

Barry C Goldstein

Dominick Anthony Zumbo

Asser Nasreldin Tantawi

Liam David Comerford

Mon-Song Chen

Hanafy E Meleis

Hanafy El Sayed Meleis

A method and apparatus for performing a bit map search of the allocation state of memory pages in a computing system. A competitive search is accomplished by a pair of dedicated microprocessors, each of which implements a differently optimized search procedure, to find a bit indicating an un-allocated page in the memory. The first processor to find such a bit interrupts the other processor. The first processor then calculates the free page location and informs the computing system of the location. The other processor is responsible for updating the bit map and summary buffers.

Bit map search by competitive processors

An architecture for a low-end, high-performance switch subsystem allows the connection of a multitude of requests per link. The switch subsystem operates a cross-bar switch under the control of a controller, such as a personal computer, to connect selected ones of a plurality of input links to selected ones of a plurality of output links. A data structure for the switch subsystem is mapped to the memory of the controller. The switch subsystem comprises three switch servers, a request server, a connect server, and an acknowledge server, which perform in a pipelined fashion. An interface protocol for the switching subsystem may be adapted to various applications and allows a connect request to be either queued in the switch subsystem until the requested output link in available or the requestor is notified immediately if the requested output link is not available, so that alternate actions can be taken.

Low-end high-performance switch subsystem architecture

A communication system provides high speed transmission of data over a link, such as a fiber optic link, between a first terminal and a second terminal. The architecture and protocol permits the use of dedicated hardware such as state machines constructed of programmable array logic units, to synchronize the transmission and reception of data packets and the retransmission of designated ones of these packets in the event of a faulty transmission. Packets to be transmitted and received are stored in an array of frames in sub-windows of a memory storage window in each of the termianls, the frame number being equal to the sequence number of the data packet. By embedding sequence and status bits in each packet within control words and bits appended to each packet, the state machine in each terminal can readily track the progress of each packet so as to request acknowledgement of error-free receipt, to send an acknowledgement, to request a retransmission of a packet designated by its serial number and to distinguish a retransmitted packet from an original packet transmitted with error.

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Chappaqua, NY, United States of America

Barry C Goldstein