International Business Machines Corporation

Barry Bradley Arndt

Mark Alan Peloquin

Steven L Pratt

Karl Milton Rister

Kevin Michael Corry

Santhosh Rao

Jennifer Lane Vargus

William M Buros

A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.

Logical extended map to demonstrate core activity including L2 and L3 cache hit and miss ratio

A computer implemented method, apparatus, and computer usable program product for binding a process to a selected node of a multi-node system. Input/output activity statistics for a process are retrieved from a set of probes. The set of probes detects a flow of data through an input/output device utilized by the process. A topology of the multi-node system that comprises a location of the input/output device is identified. A node is selected according to a decision policy to form a selected node. The process is bound to the selected node according to the decision policy.

Binding processes in a non-uniform memory access system

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Round Rock, TX, United States of America

Barry Bradley Arndt