Nvidia Corporation

Other

Barry A Wagner

Russell R Newcomb

Jonah Matthew Alben

Anthony Michael Tamasi

Alok Gupta

William B Simms

Hans Wolfgang Schulze

David G Reed

Andrew R Bell

Thomas Edward Dewey

Joseph Greco

Ashfaq Shaikh

Bruce H Lam

Simon A Thomas

Jeffrey J Irwin

Sonny S Yeoh

Saurabh Gupta

Larry Fiedler

John Stephen Montrym

Sean Jeffrey Treichler

Ludger Mimberg

William Tsu

Ting Ku

Don Le

David A Bachman

Weijen Chao

Mau Lao

The present invention facilitates efficient and effective utilization of storage management features. In one embodiment, a memory device comprises a memory interface, an ECC generation component, and storage components. The memory interface is configured to receive an access request to an address at which data is stored. The memory interface can also forward responses to the request including the data and ECC information associated with the data. The ECC generation component is configured to automatically establish an address at which the ECC information is stored based upon the receipt of the access request to an address at which data is stored. In one exemplary implementation, the internal establishment of the address at which the ECC information is stored is automatic. The storage components are configured to store the information.

Memory management systems and methods

A memory controller and a dynamic random access memory (DRAM) interface are disclosed. The memory controller implements signals for the DRAM interface. The DRAM interface includes a differential clock signal, an uncalibrated parallel command bus, and a high-speed, serial address bus. The command bus may be used to initiate communication with the memory device upon power-up and to initiate calibration of the address bus.

Memory controller and a dynamic random access memory interface

An interface for implementing a loopback configuration which offers improved calibration and/or testing of an electronic system is disclosed. More specifically, embodiments provide a bi-directional interface with at least two portions or partitions capable of communicating data in opposite directions and implementing a loopback configuration between components of an electronic system, thereby enabling more flexible, efficient and effective calibration and/or testing of the electronic system using a single interface. The loopback of the partitioned bi-directional interface may be used to perform data link training and/or electronic system testing. In one embodiment, the loopback configuration of the interface may be reversible. Additionally, the looped or coupled end of the partitions may be switched from one component to another, thereby reversing the configuration of the loopback in one embodiment. As such, embodiments enable different and/or additional calibration operations and/or tests to be performed when compared with conventional loopback configurations.

Loopback configuration for bi-directional interfaces

A memory controller includes first and second output modules for driving first and second data, respectively, to be written to a memory device. The memory controller also includes a clock module for providing an internal clock signal and a timing control module for producing a first and second timing control signals. The first and second timing control signals are supplied to the first and second output modules, respectively.

Memory device synchronization

The present invention pertains to a configurable PCI-Express switch. The configurable PCI-Express switch includes a differential I/O interface capable of being configured in a first configuration or a second configuration. In the first configuration, the differential I/O interface implements a PCI-Express interface with a coupled device. In the second configuration, the differential I/O interface implements a differential interface other than PCI-Express with the coupled device. The configurable PCI-Express switch also includes a switching unit capable of configuring the differential I/O interface in the first configuration or the second configuration.

System and method for configurable digital communication

The present invention pertains to a graphics processing unit. The graphics processing unit includes a graphics processing core configured for graphics processing. A single-ended I/O interface configured to implement single-ended communication with a frame buffer memory is included in the graphics processing unit. The graphics processing unit further includes a differential I/O interface having a first portion and a second portion. In a first configuration, the first portion and the second portion implement a PCI-Express interface with a computer system. In a second configuration, the first portion implements a PCI-Express interface with the computer system and the second portion implements differential communication with a coupled device.

Configurable GPU and method for graphics processing using a configurable GPU

A memory hub permits a graphics processor to access random access memories, such as dynamic random access memories (DRAMs). In one implementation, the memory hub permits an increase in effective memory bandwidth by aggregating the memory of two or more memories. In another implementation, the memory hub permits a graphics processor to offload memory access interfacing operations to the memory hub.

Apparatus, system, and method for graphics memory hub

A synchronous memory device is configured to switch into and out of a full speed mode to change speed the speed of data transactions without significantly disturbing the frequency of a clock input to a PLL or DLL that provides the internal clock for the synchronous memory device. Since the PLL or DLL receives a clock signal whether or not the synchronous memory device is in a non-full speed mode, the PLL or DLL does not need to settle or relock when the clock signal is reapplied to exit a different speed mode and return to the full speed mode. Therefore, the latency incurred to switch into and out of different speed modes is reduced by eliminating or substantially reducing the time for settling or relocking the PLL or DLL.

Low latency synchronous memory performance switching

Low latency synchronous memory performance switching with drift refresh

Low latency synchronous memory performance switching using update control

The present invention pertains to a computer chassis with improved airflow to reduce the occurrence of trapped air pockets and increase heat transfer from components within the chassis. The computer chassis includes a plurality of chambers, wherein each of the chambers is separated by a partition. The partitions are operable to reduce the occurrence of trapped air pockets and increase heat transfer from components of the chassis by causing air to flow through each of the chambers. The computer chassis further includes at least two air vents, wherein each of the chambers is coupled to at least one of the at least two air vents through which air enters the chamber, and wherein each of the chambers is coupled to at least one of the at least two air vents through which air exits the chamber.

Computer chassis with partitions for improved airflow

Disclosed are embodiments that may facilitate management of operation of an integrated circuit (IC) including adjustment of the IC. The adjustment may be based at least in part on a proximity of a temperature of the IC relative to a predetermined temperature.

Management of operation of an integrated circuit

Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.

Dynamic memory clock adjustments

Embodiments of power management modes for memory devices are disclosed.

Growing community of inventors

San Jose, CA, United States of America

Barry A Wagner